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Tsirkin" , Nicholas Piggin , Leif Lindholm , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org, Laurent Vivier , Alexander Gordeev References: <20241125140535.4526-1-philmd@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 25/11/24 15:14, Peter Maydell wrote: > On Mon, 25 Nov 2024 at 14:06, Philippe Mathieu-Daudé wrote: >> >> This series aims to remove a legacy field from >> MachineClass. >> >> Rather than a global exposed to all machines, >> use a pci-bus specific flag on each machine >> requiering it. > > Should this be a property of the PCI controller, rather > than on the PCI bus? Presumably on the machines that > don't allow a 0 PCI BAR address this happens because the > PCI controller refuses to map BARs at that address. > > TBH the commit message for e402463073 suggests to me > that "allow address zero" should be the default and > either specific machines should forbid it or else we > should figure out what goes wrong with them, if the > problem is caused by some bug in QEMU. The commit message's > mention of "fix PCI memory priorities" suggests to me > that this is a QEMU bug, and that it ought to be possible > to have the machine set up such that you *can* map the > BAR at address 0, it's merely invisible to the guest because > some other machine devices have higher priority and are > visible "on top" of it instead. You are probably right, the following comment ...: pcibus_t pci_bar_address(PCIDevice *d, int reg, uint8_t type, pcibus_t size) { ... /* NOTE: we do not support wrapping */ /* XXX: as we cannot support really dynamic mappings, we handle specific values as invalid mappings. */ if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || (!allow_0_address && new_addr == 0)) { return PCI_BAR_UNMAPPED; } ... is from 20 years ago at the beginning of PCI in QEMU, commit 0ac32c8375 ("PCI interrupt support - PCI BIOS interrupt remapping - more accurate memory mapping - 'info pci' monitor command") which suggest the implementation is incomplete here.