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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482e27ab569sm8617295f8f.16.2026.08.27.05.25.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Aug 2026 05:25:16 -0700 (PDT) Message-ID: <74a383fb-e124-44ea-95d7-63c6add2a53c@redhat.com> Date: Thu, 27 Aug 2026 14:25:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC v5 09/28] hw/arm/smmu: Add PTE NS/NSTable helpers To: Tao Tang , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Mostafa Saleh , Chao Liu , Jim MacArthur References: <20260813161515.2788900-1-tangtao1634@phytium.com.cn> <20260813162446.2806393-4-tangtao1634@phytium.com.cn> From: Eric Auger In-Reply-To: <20260813162446.2806393-4-tangtao1634@phytium.com.cn> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: NcyW7oxUk7EHXGJo16NfsZClPyhQR6PUpF_1DL-8wtA_1787833517 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 8/13/26 6:24 PM, Tao Tang wrote: > Add helper macros for NS and NSTable bits and group PTE attribute > accessors for clarity. No functional change beyond the new helpers. > > Signed-off-by: Tao Tang > Reviewed-by: Pierrick Bouvier Reviewed-by: Eric Auger Eric > --- > hw/arm/smmu-internal.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h > index d143d296f34..004abd58bca 100644 > --- a/hw/arm/smmu-internal.h > +++ b/hw/arm/smmu-internal.h > @@ -58,16 +58,27 @@ > ((level == 3) && \ > ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_PAGE)) > > +/* Stage 1 attribute fields in VMSAv8-64 Block and Page descriptors */ > +/* Non-secure bit */ > +#define PTE_NS(pte) \ > + (extract64(pte, 5, 1)) > + > /* access permissions */ > > #define PTE_AP(pte) \ > (extract64(pte, 6, 2)) > > +/* Stage 1 VMSAv8-64 Table descriptor fields */ > #define PTE_APTABLE(pte) \ > (extract64(pte, 61, 2)) > > +#define PTE_NSTABLE(pte) \ > + (extract64(pte, 63, 1)) > + > +/* Access flag: defined for both Block/Page and Table descriptors. */ > #define PTE_AF(pte) \ > (extract64(pte, 10, 1)) > + > /* > * TODO: At the moment all transactions are considered as privileged (EL1) > * as IOMMU translation callback does not pass user/priv attributes.