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diff for duplicates of <7503786.EvYhyI6sBW@diego>

diff --git a/a/1.txt b/N1/1.txt
index 416e6b9..05f8b85 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,4 +1,4 @@
-Am Montag, 27. M?rz 2023, 18:49:27 CEST schrieb Andy Chiu:
+Am Montag, 27. März 2023, 18:49:27 CEST schrieb Andy Chiu:
 > From: Greentime Hu <greentime.hu@sifive.com>
 > 
 > This patch is used to detect the size of CPU vector registers and use
@@ -27,3 +27,10 @@ Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
 
 
 Heiko
+
+
+
+_______________________________________________
+linux-riscv mailing list
+linux-riscv@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/a/content_digest b/N1/content_digest
index 92cce53..ac2964f 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,12 +1,33 @@
  "ref\020230327164941.20491-1-andy.chiu@sifive.com\0"
  "ref\020230327164941.20491-8-andy.chiu@sifive.com\0"
  "From\0Heiko St\303\274bner <heiko@sntech.de>\0"
- "Subject\0[PATCH -next v17 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context\0"
+ "Subject\0Re: [PATCH -next v17 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context\0"
  "Date\0Fri, 31 Mar 2023 13:02:52 +0200\0"
- "To\0kvm-riscv@lists.infradead.org\0"
+ "To\0linux-riscv@lists.infradead.org"
+  palmer@dabbelt.com
+  anup@brainfault.org
+  atishp@atishpatra.org
+  kvm-riscv@lists.infradead.org
+ " kvm@vger.kernel.org\0"
+ "Cc\0vineetg@rivosinc.com"
+  greentime.hu@sifive.com
+  guoren@linux.alibaba.com
+  Vincent Chen <vincent.chen@sifive.com>
+  Andy Chiu <andy.chiu@sifive.com>
+  Paul Walmsley <paul.walmsley@sifive.com>
+  Albert Ou <aou@eecs.berkeley.edu>
+  Guo Ren <guoren@kernel.org>
+  Conor Dooley <conor.dooley@microchip.com>
+  Li Zhengyu <lizhengyu3@huawei.com>
+  Xianting Tian <xianting.tian@linux.alibaba.com>
+  Masahiro Yamada <masahiroy@kernel.org>
+  Jisheng Zhang <jszhang@kernel.org>
+  Andrew Jones <ajones@ventanamicro.com>
+  Richard Henderson <richard.henderson@linaro.org>
+ " Andy Chiu <andy.chiu@sifive.com>\0"
  "\00:1\0"
  "b\0"
- "Am Montag, 27. M?rz 2023, 18:49:27 CEST schrieb Andy Chiu:\n"
+ "Am Montag, 27. M\303\244rz 2023, 18:49:27 CEST schrieb Andy Chiu:\n"
  "> From: Greentime Hu <greentime.hu@sifive.com>\n"
  "> \n"
  "> This patch is used to detect the size of CPU vector registers and use\n"
@@ -34,6 +55,13 @@
  "Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>\n"
  "\n"
  "\n"
- Heiko
+ "Heiko\n"
+ "\n"
+ "\n"
+ "\n"
+ "_______________________________________________\n"
+ "linux-riscv mailing list\n"
+ "linux-riscv@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-riscv
 
-71ec193f6ea3e330391cae7258135ad9b519f6dc84cdf7307d7705787328505c
+2a0767dfc035cfab581df88c3732faaa658457a88d8cb855065f6e377e34de83

diff --git a/a/1.txt b/N2/1.txt
index 416e6b9..327fc4b 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -1,4 +1,4 @@
-Am Montag, 27. M?rz 2023, 18:49:27 CEST schrieb Andy Chiu:
+Am Montag, 27. März 2023, 18:49:27 CEST schrieb Andy Chiu:
 > From: Greentime Hu <greentime.hu@sifive.com>
 > 
 > This patch is used to detect the size of CPU vector registers and use
diff --git a/a/content_digest b/N2/content_digest
index 92cce53..70d1418 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -1,12 +1,33 @@
  "ref\020230327164941.20491-1-andy.chiu@sifive.com\0"
  "ref\020230327164941.20491-8-andy.chiu@sifive.com\0"
  "From\0Heiko St\303\274bner <heiko@sntech.de>\0"
- "Subject\0[PATCH -next v17 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context\0"
+ "Subject\0Re: [PATCH -next v17 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context\0"
  "Date\0Fri, 31 Mar 2023 13:02:52 +0200\0"
- "To\0kvm-riscv@lists.infradead.org\0"
+ "To\0linux-riscv@lists.infradead.org"
+  palmer@dabbelt.com
+  anup@brainfault.org
+  atishp@atishpatra.org
+  kvm-riscv@lists.infradead.org
+ " kvm@vger.kernel.org\0"
+ "Cc\0vineetg@rivosinc.com"
+  greentime.hu@sifive.com
+  guoren@linux.alibaba.com
+  Vincent Chen <vincent.chen@sifive.com>
+  Andy Chiu <andy.chiu@sifive.com>
+  Paul Walmsley <paul.walmsley@sifive.com>
+  Albert Ou <aou@eecs.berkeley.edu>
+  Guo Ren <guoren@kernel.org>
+  Conor Dooley <conor.dooley@microchip.com>
+  Li Zhengyu <lizhengyu3@huawei.com>
+  Xianting Tian <xianting.tian@linux.alibaba.com>
+  Masahiro Yamada <masahiroy@kernel.org>
+  Jisheng Zhang <jszhang@kernel.org>
+  Andrew Jones <ajones@ventanamicro.com>
+  Richard Henderson <richard.henderson@linaro.org>
+ " Andy Chiu <andy.chiu@sifive.com>\0"
  "\00:1\0"
  "b\0"
- "Am Montag, 27. M?rz 2023, 18:49:27 CEST schrieb Andy Chiu:\n"
+ "Am Montag, 27. M\303\244rz 2023, 18:49:27 CEST schrieb Andy Chiu:\n"
  "> From: Greentime Hu <greentime.hu@sifive.com>\n"
  "> \n"
  "> This patch is used to detect the size of CPU vector registers and use\n"
@@ -36,4 +57,4 @@
  "\n"
  Heiko
 
-71ec193f6ea3e330391cae7258135ad9b519f6dc84cdf7307d7705787328505c
+c6a4c6bcc0038831e8aa2dc3e46a0a82b91be645790bc18ddf037d50b900d56f

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