From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80C3FC44507 for ; Fri, 17 Jul 2026 07:19:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:To:Subject:MIME-Version: Date:Message-ID:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=K/3kmKDqakVkcErwxAvLFummYnUdZWBHoZnavFpzzgU=; b=x6w4FMULPl2YpXhP03cf0yfatq qrkFM9SK5se2Jles4d0WIIui8pKF1ix3b9f3FmOTwROTX2+wv979656HmKqswFyVP+1X7815ac/BL MawdsgRYcVZj9lhVrv73/Fl6s3x+k9jg3DhDe8hzrWpiMoxJNBkMjmf/WbnNvsl256UoOuVIeshib c8zUeeHZYqgEf9GuJWt2L5ZfahHzvRqp46wirUd4T7njRTiBkzSOtzjcrtMSjmaQ4HNCWybXHiYaB l0M61mHCn5S4ko4GFbinxEkDTET/VIx8/8oyIFhW3MNXWtDo+RjaTCffrRfhw/GW5/bZTD/p/q3TN /KSaawwA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wkcr7-00000001Nv6-1Q5v; Fri, 17 Jul 2026 07:19:33 +0000 Received: from out-174.mta1.migadu.com ([95.215.58.174]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wkcr4-00000001NtV-2QUU for linux-riscv@lists.infradead.org; Fri, 17 Jul 2026 07:19:32 +0000 Message-ID: <765ac2fe-a0ff-4980-915c-b2546a85b86a@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1784272766; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oiyh43muGYb5yG7m7nFyoOnCjLjuRG2YSiAzdEsauHY=; b=w2Rw97yrn+trEb11MlepQMLUkeql4jIzLT9wpa6NXqVcPhtTNmtfsohe2mh1s4SCxOBFVd 0hRXvGoo2j0WBEZUXkoSOzVfGnY/IiEn9BhuPTS5no3cNsfxL3c3CRc8mKAFUOeGlxLYet wR65RRXYd6PXhJCmTLY8ltkv9g/0gXE= Date: Fri, 17 Jul 2026 15:19:00 +0800 MIME-Version: 1.0 Subject: Re: [PATCH v4 1/2] riscv: Introduce support for hardware break/watchpoints To: Himanshu Chauhan , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, shuah@kernel.org References: <20260518065920.872131-1-himanshu.chauhan@oss.qualcomm.com> <20260518065920.872131-2-himanshu.chauhan@oss.qualcomm.com> X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Qingfang Deng In-Reply-To: <20260518065920.872131-2-himanshu.chauhan@oss.qualcomm.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260717_001930_898335_2BD26A37 X-CRM114-Status: GOOD ( 18.09 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SGksCgpPbiAyMDI2LzUvMTggMTQ6NTksIEhpbWFuc2h1IENoYXVoYW4gd3JvdGU6Cj4gZGlmZiAt LWdpdCBhL2FyY2gvcmlzY3Yva2VybmVsL2h3X2JyZWFrcG9pbnQuYyBiL2FyY2gvcmlzY3Yva2Vy bmVsL2h3X2JyZWFrcG9pbnQuYwo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAw MDAwMDAwLi4zNDU1NmE4ZjNjOWIKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvYXJjaC9yaXNjdi9r ZXJuZWwvaHdfYnJlYWtwb2ludC5jCj4gQEAgLTAsMCArMSw3MzYgQEAKPiArLy8gU1BEWC1MaWNl bnNlLUlkZW50aWZpZXI6IEdQTC0yLjAtb25seQo+ICsvKgo+ICsgKiBDb3B5cmlnaHQgKEMpIDIw MjYgUXVhbGNvbW0gVGVjaG5vbG9naWVzLCBJbmMuCj4gKyAqLwo+ICsKClRvIG1ha2UgeW91ciBs b2dzIG1vcmUgaW5mb3JtYXRpdmUsIHlvdSBtYXkgd2FudCB0byAjZGVmaW5lIHByX2ZtdCBoZXJl LgoKRm9yIGV4YW1wbGU6IGAjZGVmaW5lIHByX2ZtdChmbXQpIEtCVUlMRF9NT0ROQU1FICI6ICIg Zm10YCB3aWxsIHByZWZpeCAKYWxsIHlvdXIgbG9ncyB3aXRoICJod19icmVha3BvaW50OiAiLgoK PiArI2luY2x1ZGUgPGxpbnV4L2h3X2JyZWFrcG9pbnQuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3Bl cmZfZXZlbnQuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3NwaW5sb2NrLmg+Cj4gKyNpbmNsdWRlIDxs aW51eC9wZXJjcHUuaD4KPiArI2luY2x1ZGUgPGxpbnV4L2tkZWJ1Zy5oPgo+ICsjaW5jbHVkZSA8 bGludXgvYml0b3BzLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9jcHUuaD4KPiArI2luY2x1ZGUgPGxp bnV4L2NwdWhvdHBsdWcuaD4KPiArCj4gKyNpbmNsdWRlIDxhc20vc2JpLmg+Cj4gKwo+ICsvKiBS ZWdpc3RlcmVkIHBlci1jcHUgYnAvd3AgKi8KPiArc3RhdGljIERFRklORV9QRVJfQ1BVKHN0cnVj dCBwZXJmX2V2ZW50ICosIHBjcHVfaHdfYnBfZXZlbnRzW1JJU0NWX0hXX0JQX05VTV9NQVhdKTsK PiArc3RhdGljIERFRklORV9QRVJfQ1BVKHVuc2lnbmVkIGxvbmcsIGVjYWxsX2xvY2tfZmxhZ3Mp Owo+ICtzdGF0aWMgREVGSU5FX1BFUl9DUFUocmF3X3NwaW5sb2NrX3QsIGVjYWxsX2xvY2spOwo+ ICsKPiArLyogUGVyLWNwdSBzaGFyZWQgbWVtb3J5IGJldHdlZW4gUyBhbmQgTSBtb2RlICovCj4g K3N0YXRpYyB1bmlvbiBzYmlfZGJ0cl9zaG1lbV9lbnRyeSBfX3BlcmNwdSAqc2JpX2RidHJfc2ht ZW07Cj4gKwo+ICsvKiBudW1iZXIgb2YgZGVidWcgdHJpZ2dlcnMgb24gdGhpcyBjcHUgLiAqLwo+ ICtzdGF0aWMgaW50IGRidHJfdG90YWxfbnVtIF9fcm9fYWZ0ZXJfaW5pdDsKPiArc3RhdGljIGlu dCBkYnRyX3R5cGUgX19yb19hZnRlcl9pbml0Owo+ICtzdGF0aWMgaW50IGRidHJfaW5pdCBfX3Jv X2FmdGVyX2luaXQ7Cj4gKwo+ICsjaWYgX19yaXNjdl94bGVuID09IDY0Cj4gKyNkZWZpbmUgTUVN X0hJKF9tKQkwCj4gKyNkZWZpbmUgTUVNX0xPKF9tKQkoKHU2NCkoX20pKQo+ICsjZWxpZiBfX3Jp c2N2X3hsZW4gPT0gMzIKPiArI2RlZmluZSBNRU1fSEkoX20pCSgodTY0KShfbSkgPj4gMzIpCj4g KyNkZWZpbmUgTUVNX0xPKF9tKQkoKHU2NCkoX20pICYgMHhGRkZGRkZGRlVMKQo+ICsjZWxzZQo+ ICsjZXJyb3IgIlVua25vd24gX19yaXNjdl94bGVuIgo+ICsjZW5kaWYKPiArCj4gK3N0YXRpYyBp bnQgYXJjaF9zbXBfc2V0dXBfc2JpX3NobWVtKHVuc2lnbmVkIGludCBjcHUpCj4gK3sKPiArCXVu aW9uIHNiaV9kYnRyX3NobWVtX2VudHJ5ICpkYnRyX3NobWVtOwo+ICsJdW5zaWduZWQgbG9uZyBz aG1lbV9wYTsKTml0OiB0aGUgdHlwZSBvZiBhIHBoeXNpY2FsIGFkZHJlc3Mgc2hvdWxkIGJlICJw aHlzX2FkZHJfdCIuCj4gKwlzdHJ1Y3Qgc2JpcmV0IHJldDsKPiArCWludCByYyA9IDA7Cj4gKwo+ ICsJZGJ0cl9zaG1lbSA9IHBlcl9jcHVfcHRyKHNiaV9kYnRyX3NobWVtLCBjcHUpOwo+ICsJaWYg KCFkYnRyX3NobWVtKSB7Cj4gKwkJcHJfZXJyKCJJbnZhbGlkIHBlci1jcHUgc2hhcmVkIG1lbW9y eSBmb3IgZGVidWcgdHJpZ2dlcnNcbiIpOwo+ICsJCXJldHVybiAtRU5PREVWOwo+ICsJfQo+ICsK PiArCXNobWVtX3BhID0gX19wYShkYnRyX3NobWVtKTsKCkl0J3Mgbm90IHNhZmUgdG8gZ2V0IHRo ZSBwaHlzaWNhbCBhZGRyZXNzIG9mIGEgcGVyY3B1LWFsbG9jYXRlZCBwb2ludGVyIAp3aXRoIF9f cGEoKSwgYXMgaXQgbWF5IGJlIGEgdm1hbGxvYygpJ2QgcG9pbnRlci4gUGxlYXNlIHVzZSAKcGVy X2NwdV9wdHJfdG9fcGh5cygpIGluc3RlYWQuCgpBbHNvLCBldmVuwqBwZXJfY3B1X3B0cl90b19w aHlzKCkgd2lsbCBicmVha8KgaWYgdGhlIGFsbG9jYXRpb24gc2l6ZSBpcyAKbGFyZ2VyIHRoYW4g dGhlIHBhZ2Ugc2l6ZSwgYXMgaXQgb25seSByZXR1cm5zIHRoZSBwaHlzaWNhbCBhZGRyZXNzIG9m IAp0aGUgdmVyeSBmaXJzdCBwYWdlLgoKPiArCj4gKwlyZXQgPSBzYmlfZWNhbGwoU0JJX0VYVF9E QlRSLCBTQklfRVhUX0RCVFJfU0VUVVBfU0hNRU0sCj4gKwkJCU1FTV9MTyhzaG1lbV9wYSksIE1F TV9ISShzaG1lbV9wYSksIDAsIDAsIDAsIDApOwo+ICsKPiArCWlmIChyZXQuZXJyb3IpIHsKPiAr CQlzd2l0Y2ggKHJldC5lcnJvcikgewo+ICsJCWNhc2UgU0JJX0VSUl9ERU5JRUQ6Cj4gKwkJCXBy X3dhcm4oIkFjY2VzcyBkZW5pZWQgZm9yIHNoYXJlZCBtZW1vcnkgYXQgJWx4XG4iLAo+ICsJCQkJ c2htZW1fcGEpOwo+ICsJCQlyYyA9IC1FUEVSTTsKPiArCQkJYnJlYWs7Cj4gKwo+ICsJCWNhc2Ug U0JJX0VSUl9JTlZBTElEX1BBUkFNOgo+ICsJCWNhc2UgU0JJX0VSUl9JTlZBTElEX0FERFJFU1M6 Cj4gKwkJCXByX3dhcm4oIkludmFsaWQgYWRkcmVzcyBwYXJhbWV0ZXIgKCVsdSlcbiIsCj4gKwkJ CQlyZXQuZXJyb3IpOwo+ICsJCQlyYyA9IC1FSU5WQUw7Cj4gKwkJCWJyZWFrOwo+ICsKPiArCQlj YXNlIFNCSV9FUlJfQUxSRUFEWV9BVkFJTEFCTEU6Cj4gKwkJCXByX3dhcm4oIlNoYXJlZCBtZW1v cnkgaXMgYWxyZWFkeSBzZXRcbiIpOwo+ICsJCQlyYyA9IC1FQUREUklOVVNFOwo+ICsJCQlicmVh azsKPiArCj4gKwkJY2FzZSBTQklfRVJSX0ZBSUxVUkU6Cj4gKwkJCXByX2VycigiSW50ZXJuYWwg c2R0cmlnIHN0YXRlIGVycm9yXG4iKTsKPiArCQkJcmMgPSAtRU5YSU87Cj4gKwkJCWJyZWFrOwo+ ICsKPiArCQlkZWZhdWx0Ogo+ICsJCQlwcl93YXJuKCJVbmtub3duIGVycm9yICVsdVxuIiwgcmV0 LmVycm9yKTsKPiArCQkJcmMgPSAtRU5YSU87Cj4gKwkJCWJyZWFrOwo+ICsJCX0KPiArCX0KPiAr Cj4gKwlwcl9pbmZvKCJDUFUgJWQ6IEhXIEJyZWFrcG9pbnQgc2hhcmVkIG1lbW9yeSByZWdpc3Rl cmVkLlxuIiwgY3B1KTsKVGhpcyB3aWxsIGJlIHByaW50ZWQgZXZlbiBpZiBhbiBlcnJvciBvY2N1 cnMuIFBsZWFzZSBtb3ZlIGl0IGludG8gdGhlIApgZWxzZWAgYmxvY2sgb2YgYGlmIChyZXQuZXJy b3IpYC4KPiArCj4gKwlyZXR1cm4gcmM7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgYXJjaF9zbXBf dGVhcmRvd25fc2JpX3NobWVtKHVuc2lnbmVkIGludCBjcHUpCj4gK3sKPiArCXN0cnVjdCBzYmly ZXQgcmV0Owo+ICsKPiArCS8qIERpc2FibGUgc2hhcmVkIG1lbW9yeSAqLwo+ICsJcmV0ID0gc2Jp X2VjYWxsKFNCSV9FWFRfREJUUiwgU0JJX0VYVF9EQlRSX1NFVFVQX1NITUVNLAo+ICsJCQktMVVM LCAtMVVMLCAwLCAwLCAwLCAwKTsKPiArCj4gKwlpZiAocmV0LmVycm9yKSB7Cj4gKwkJc3dpdGNo IChyZXQuZXJyb3IpIHsKPiArCQljYXNlIFNCSV9FUlJfREVOSUVEOgo+ICsJCQlwcl9lcnIoIkFj Y2VzcyBkZW5pZWQgZm9yIHNoYXJlZCBtZW1vcnkuXG4iKTsKPiArCQkJYnJlYWs7Cj4gKwo+ICsJ CWNhc2UgU0JJX0VSUl9JTlZBTElEX1BBUkFNOgo+ICsJCWNhc2UgU0JJX0VSUl9JTlZBTElEX0FE RFJFU1M6Cj4gKwkJCXByX2VycigiSW52YWxpZCBhZGRyZXNzIHBhcmFtZXRlciAoJWx1KVxuIiwg cmV0LmVycm9yKTsKPiArCQkJYnJlYWs7Cj4gKwo+ICsJCWNhc2UgU0JJX0VSUl9BTFJFQURZX0FW QUlMQUJMRToKPiArCQkJcHJfZXJyKCJTaGFyZWQgbWVtb3J5IGlzIGFscmVhZHkgc2V0XG4iKTsK PiArCQkJYnJlYWs7Cj4gKwkJY2FzZSBTQklfRVJSX0ZBSUxVUkU6Cj4gKwkJCXByX2VycigiSW50 ZXJuYWwgc2R0cmlnIHN0YXRlIGVycm9yXG4iKTsKPiArCQkJYnJlYWs7Cj4gKwkJZGVmYXVsdDoK PiArCQkJcHJfZXJyKCJVbmtub3duIGVycm9yICVsdVxuIiwgcmV0LmVycm9yKTsKPiArCQkJYnJl YWs7Cj4gKwkJfQo+ICsJfQo+ICsKPiArCXByX3dhcm4oIkNQVSAlZDogSFcgQnJlYWtwb2ludCBz aGFyZWQgbWVtb3J5IGRpc2FibGVkLlxuIiwgY3B1KTsKRGl0dG8uCj4gKwo+ICsJcmV0dXJuIDA7 Cj4gK30KCkJlc3QgcmVnYXJkcywKClFpbmdmYW5nCgoKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KbGludXgtcmlzY3YgbWFpbGluZyBsaXN0CmxpbnV4LXJp c2N2QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1h bi9saXN0aW5mby9saW51eC1yaXNjdgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-178.mta1.migadu.com (out-178.mta1.migadu.com [95.215.58.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No 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header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=w2Rw97yr; arc=none smtp.client-ip=95.215.58.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="w2Rw97yr" Message-ID: <765ac2fe-a0ff-4980-915c-b2546a85b86a@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1784272766; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oiyh43muGYb5yG7m7nFyoOnCjLjuRG2YSiAzdEsauHY=; b=w2Rw97yrn+trEb11MlepQMLUkeql4jIzLT9wpa6NXqVcPhtTNmtfsohe2mh1s4SCxOBFVd 0hRXvGoo2j0WBEZUXkoSOzVfGnY/IiEn9BhuPTS5no3cNsfxL3c3CRc8mKAFUOeGlxLYet wR65RRXYd6PXhJCmTLY8ltkv9g/0gXE= Date: Fri, 17 Jul 2026 15:19:00 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v4 1/2] riscv: Introduce support for hardware break/watchpoints To: Himanshu Chauhan , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, shuah@kernel.org References: <20260518065920.872131-1-himanshu.chauhan@oss.qualcomm.com> <20260518065920.872131-2-himanshu.chauhan@oss.qualcomm.com> X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Qingfang Deng In-Reply-To: <20260518065920.872131-2-himanshu.chauhan@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT Hi, On 2026/5/18 14:59, Himanshu Chauhan wrote: > diff --git a/arch/riscv/kernel/hw_breakpoint.c b/arch/riscv/kernel/hw_breakpoint.c > new file mode 100644 > index 000000000000..34556a8f3c9b > --- /dev/null > +++ b/arch/riscv/kernel/hw_breakpoint.c > @@ -0,0 +1,736 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2026 Qualcomm Technologies, Inc. > + */ > + To make your logs more informative, you may want to #define pr_fmt here. For example: `#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt` will prefix all your logs with "hw_breakpoint: ". > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +/* Registered per-cpu bp/wp */ > +static DEFINE_PER_CPU(struct perf_event *, pcpu_hw_bp_events[RISCV_HW_BP_NUM_MAX]); > +static DEFINE_PER_CPU(unsigned long, ecall_lock_flags); > +static DEFINE_PER_CPU(raw_spinlock_t, ecall_lock); > + > +/* Per-cpu shared memory between S and M mode */ > +static union sbi_dbtr_shmem_entry __percpu *sbi_dbtr_shmem; > + > +/* number of debug triggers on this cpu . */ > +static int dbtr_total_num __ro_after_init; > +static int dbtr_type __ro_after_init; > +static int dbtr_init __ro_after_init; > + > +#if __riscv_xlen == 64 > +#define MEM_HI(_m) 0 > +#define MEM_LO(_m) ((u64)(_m)) > +#elif __riscv_xlen == 32 > +#define MEM_HI(_m) ((u64)(_m) >> 32) > +#define MEM_LO(_m) ((u64)(_m) & 0xFFFFFFFFUL) > +#else > +#error "Unknown __riscv_xlen" > +#endif > + > +static int arch_smp_setup_sbi_shmem(unsigned int cpu) > +{ > + union sbi_dbtr_shmem_entry *dbtr_shmem; > + unsigned long shmem_pa; Nit: the type of a physical address should be "phys_addr_t". > + struct sbiret ret; > + int rc = 0; > + > + dbtr_shmem = per_cpu_ptr(sbi_dbtr_shmem, cpu); > + if (!dbtr_shmem) { > + pr_err("Invalid per-cpu shared memory for debug triggers\n"); > + return -ENODEV; > + } > + > + shmem_pa = __pa(dbtr_shmem); It's not safe to get the physical address of a percpu-allocated pointer with __pa(), as it may be a vmalloc()'d pointer. Please use per_cpu_ptr_to_phys() instead. Also, even per_cpu_ptr_to_phys() will break if the allocation size is larger than the page size, as it only returns the physical address of the very first page. > + > + ret = sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_SETUP_SHMEM, > + MEM_LO(shmem_pa), MEM_HI(shmem_pa), 0, 0, 0, 0); > + > + if (ret.error) { > + switch (ret.error) { > + case SBI_ERR_DENIED: > + pr_warn("Access denied for shared memory at %lx\n", > + shmem_pa); > + rc = -EPERM; > + break; > + > + case SBI_ERR_INVALID_PARAM: > + case SBI_ERR_INVALID_ADDRESS: > + pr_warn("Invalid address parameter (%lu)\n", > + ret.error); > + rc = -EINVAL; > + break; > + > + case SBI_ERR_ALREADY_AVAILABLE: > + pr_warn("Shared memory is already set\n"); > + rc = -EADDRINUSE; > + break; > + > + case SBI_ERR_FAILURE: > + pr_err("Internal sdtrig state error\n"); > + rc = -ENXIO; > + break; > + > + default: > + pr_warn("Unknown error %lu\n", ret.error); > + rc = -ENXIO; > + break; > + } > + } > + > + pr_info("CPU %d: HW Breakpoint shared memory registered.\n", cpu); This will be printed even if an error occurs. Please move it into the `else` block of `if (ret.error)`. > + > + return rc; > +} > + > +static int arch_smp_teardown_sbi_shmem(unsigned int cpu) > +{ > + struct sbiret ret; > + > + /* Disable shared memory */ > + ret = sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_SETUP_SHMEM, > + -1UL, -1UL, 0, 0, 0, 0); > + > + if (ret.error) { > + switch (ret.error) { > + case SBI_ERR_DENIED: > + pr_err("Access denied for shared memory.\n"); > + break; > + > + case SBI_ERR_INVALID_PARAM: > + case SBI_ERR_INVALID_ADDRESS: > + pr_err("Invalid address parameter (%lu)\n", ret.error); > + break; > + > + case SBI_ERR_ALREADY_AVAILABLE: > + pr_err("Shared memory is already set\n"); > + break; > + case SBI_ERR_FAILURE: > + pr_err("Internal sdtrig state error\n"); > + break; > + default: > + pr_err("Unknown error %lu\n", ret.error); > + break; > + } > + } > + > + pr_warn("CPU %d: HW Breakpoint shared memory disabled.\n", cpu); Ditto. > + > + return 0; > +} Best regards, Qingfang