From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sandipan Das Subject: Re: [PATCH bpf-next 2/7] ppc: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_* Date: Wed, 5 Dec 2018 12:07:54 +0530 Message-ID: <7664a4d2-ed4e-4e60-2d1d-3b113d05972b@linux.ibm.com> References: <1543956922-8620-1-git-send-email-jiong.wang@netronome.com> <1543956922-8620-3-git-send-email-jiong.wang@netronome.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: daniel@iogearbox.net, ast@kernel.org, netdev@vger.kernel.org, oss-drivers@netronome.com, "Naveen N . Rao" To: Jiong Wang Return-path: Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:53342 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726037AbeLEGiD (ORCPT ); Wed, 5 Dec 2018 01:38:03 -0500 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id wB56Shmv146719 for ; Wed, 5 Dec 2018 01:38:02 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2p66tgehh8-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 05 Dec 2018 01:38:01 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 5 Dec 2018 06:38:00 -0000 In-Reply-To: <1543956922-8620-3-git-send-email-jiong.wang@netronome.com> Content-Language: en-US Sender: netdev-owner@vger.kernel.org List-ID: Hi Jiong, On 05/12/18 2:25 AM, Jiong Wang wrote: > This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*. > > Cc: Naveen N. Rao > Cc: Sandipan Das > Signed-off-by: Jiong Wang > --- [...] > diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c > index 17482f5..c685b4f 100644 > --- a/arch/powerpc/net/bpf_jit_comp64.c > +++ b/arch/powerpc/net/bpf_jit_comp64.c > @@ -529,9 +529,15 @@ static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, > if (imm != 0) > PPC_SRDI(dst_reg, dst_reg, imm); > break; > + case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */ > + PPC_SRAW(dst_reg, dst_reg, src_reg); > + break; On ppc64, the sraw and srawi instructions also use sign extension. So, you will have to ensure that upper 32 bits are cleared. We already have a label in our JIT code called bpf_alu32_trunc that takes care of this. Replacing the break statement with a goto bpf_alu32_trunc will fix this. > case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */ > PPC_SRAD(dst_reg, dst_reg, src_reg); > break; > + case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */ > + PPC_SRAWI(dst_reg, dst_reg, imm); > + break; Same here. > case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */ > if (imm != 0) > PPC_SRADI(dst_reg, dst_reg, imm); > With Regards, Sandipan