From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39E3CC2D0D1 for ; Mon, 24 Jun 2024 09:05:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C2A4810E3BB; Mon, 24 Jun 2024 09:05:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=tq-group.com header.i=@tq-group.com header.b="lqdhjwPP"; dkim=fail reason="key not found in DNS" (0-bit key; unprotected) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="iEhS3ReE"; dkim-atps=neutral Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by gabe.freedesktop.org (Postfix) with ESMTPS id 367E010E3BB for ; Mon, 24 Jun 2024 09:05:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1719219913; x=1750755913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VqCfgoxgOh2LjZAmQamcpHdT2Mvt8Dlz0W/VWPw3SoY=; b=lqdhjwPPaxQeaWWDIrMvk1/+ONNIcJBtw3nHgM3/IDqXlqmy8FjT/9od wvv8ECLfeAB3Bg5EOtOIvemsTQDrKSv302LuYFeFm18Za6oM0fHujVseB E/x2qffkoOtJP3BS8Fgy1eCR9AAIY/mUrXt+MglCUnFkuptl4zDHGgsz2 wDQxkdK0LTbit4ggRa7Z3TlbhEEQo/cm5zMLcV7+Qotr13alisfXTbiF/ u9eFg0+tP+N1+y0cC/a2eWTydt2uTdE/a9C1xkv2GY6byG3CfYMiSbbCo plmICCFbq3Qrdml/UhXoA0XpX9kEbmz0cibg/cLKJNjoSRm3O6mMMr4EK w==; X-CSE-ConnectionGUID: VLXWlxuLQYe9SGW2NuYrTA== X-CSE-MsgGUID: NMdtG+O0Q8+f/x0tMVfVxQ== X-IronPort-AV: E=Sophos;i="6.08,261,1712613600"; d="scan'208";a="37547142" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 24 Jun 2024 11:05:11 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 59187164F2F; Mon, 24 Jun 2024 11:05:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1719219907; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=VqCfgoxgOh2LjZAmQamcpHdT2Mvt8Dlz0W/VWPw3SoY=; b=iEhS3ReErpOmFtGYhB5rRsDNAQDJ5EDvtkxZOC0h5ps2zo7ddn6cCPxJOPAYrlhqYVqXjO /02/F+za/LBFOlGFIhjZ9m1G81iG2As5osfnyjgShlkqhA2PqxP7vHCEAf59z1Bo+mIrnG IIJLldB5YrfmFizTOXFZutIgmbnNfrbXvhgKBsqnxHpSm8DcEkn+2Lol9cmBRHwKHheSbW a9gdwbaQwAMhyTEbOcUQ7gfvOczDlSaKlhxasyu3RJvopqC1Ng9MFYoK2GcTxJKx01yOkZ 6Ec2nO0iNdpoKtNGISXs3A3OTMy0tYWAkgMzS2bF+47Xu8ro7dj5b4KQ7ZODcQ== From: Alexander Stein To: dri-devel@lists.freedesktop.org Cc: Marek Vasut , Andrzej Hajda , Daniel Vetter , David Airlie , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Lucas Stach , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Robert Foss , Thomas Zimmermann , kernel@dh-electronics.com, Marek Vasut Subject: Re: [PATCH v3 2/6] drm/bridge: tc358767: Use tc_pxl_pll_calc() to correct adjusted_mode clock Date: Mon, 24 Jun 2024 11:05:08 +0200 Message-ID: <7681391.EvYhyI6sBW@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20240623143846.12603-2-marex@denx.de> References: <20240623143846.12603-1-marex@denx.de> <20240623143846.12603-2-marex@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Am Sonntag, 23. Juni 2024, 16:38:34 CEST schrieb Marek Vasut: > Use tc_pxl_pll_calc() to find out the exact clock frequency generated by = the > Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency a= nd > pass it down the display pipeline to obtain exactly this frequency on inp= ut > into this bridge. >=20 > The precise input frequency that matches the Pixel PLL frequency is > important for this bridge, as if the frequencies do not match, the > bridge does suffer VFIFO overruns or underruns. >=20 > Signed-off-by: Marek Vasut This changes actually changes the media_disp1_pix clock to match the configured PLL rate in the bridge. 147333000 instead of 148500000. Reviewed-by: Alexander Stein > --- > Cc: Andrzej Hajda > Cc: Daniel Vetter > Cc: David Airlie > Cc: Jernej Skrabec > Cc: Jonas Karlman > Cc: Laurent Pinchart > Cc: Lucas Stach > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Neil Armstrong > Cc: Robert Foss > Cc: Thomas Zimmermann > Cc: dri-devel@lists.freedesktop.org > Cc: kernel@dh-electronics.com > --- > V2: - Use mode clock as input into tc_pxl_pll_calc() to avoid > accumulating rounding error > V3: No change > --- > drivers/gpu/drm/bridge/tc358767.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) >=20 > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/t= c358767.c > index cbb342d811ac3..20be21660ba76 100644 > --- a/drivers/gpu/drm/bridge/tc358767.c > +++ b/drivers/gpu/drm/bridge/tc358767.c > @@ -1619,6 +1619,18 @@ static int tc_dpi_atomic_check(struct drm_bridge *= bridge, > struct drm_crtc_state *crtc_state, > struct drm_connector_state *conn_state) > { > + struct tc_data *tc =3D bridge_to_tc(bridge); > + int adjusted_clock =3D 0; > + int ret; > + > + ret =3D tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), > + crtc_state->mode.clock * 1000, > + &adjusted_clock, NULL); > + if (ret) > + return ret; > + > + crtc_state->adjusted_mode.clock =3D adjusted_clock / 1000; > + > /* DSI->DPI interface clock limitation: upto 100 MHz */ > if (crtc_state->adjusted_mode.clock > 100000) > return -EINVAL; > @@ -1631,6 +1643,18 @@ static int tc_edp_atomic_check(struct drm_bridge *= bridge, > struct drm_crtc_state *crtc_state, > struct drm_connector_state *conn_state) > { > + struct tc_data *tc =3D bridge_to_tc(bridge); > + int adjusted_clock =3D 0; > + int ret; > + > + ret =3D tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), > + crtc_state->mode.clock * 1000, > + &adjusted_clock, NULL); > + if (ret) > + return ret; > + > + crtc_state->adjusted_mode.clock =3D adjusted_clock / 1000; > + > /* DPI->(e)DP interface clock limitation: upto 154 MHz */ > if (crtc_state->adjusted_mode.clock > 154000) > return -EINVAL; >=20 =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/