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Wed, 09 Sep 2026 03:27:59 -0700 (PDT) Received: from ehlo.thunderbird.net ([62.214.191.67]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4859162f354sm35595207f8f.20.2026.09.09.03.27.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Sep 2026 03:27:58 -0700 (PDT) Date: Wed, 09 Sep 2026 10:27:57 +0000 From: Bernhard Beschow To: qemu-devel@nongnu.org, Bin Meng , QEMU CC: Jean-Christophe Dubois , Peter Maydell , qemu-arm@nongnu.org Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_03/10=5D_hw/arm=3A_fsl-imx6ul=3A_M?= =?US-ASCII?Q?ap_early_firmware_register_placeholders?= In-Reply-To: <20260812013619.2134092-4-bin.meng@processmission.com> References: <20260812013619.2134092-1-bin.meng@processmission.com> <20260812013619.2134092-4-bin.meng@processmission.com> Message-ID: <768450BF-240E-4E73-99FF-E234915C066A@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=shentey@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Am 12=2E August 2026 01:36:06 UTC schrieb Bin Meng : >U-Boot configures the AIPS bus access controls and the i=2EMX6UL SNVS >low-power registers before its console is available=2E Its timer setup >also enables the system counter through the control window on AIPS2=2E > >These blocks are not modeled yet=2E Map unimplemented regions at their >documented addresses so early firmware accesses complete without >falling through to unmapped memory=2E Hi Bin, You could try setting mc->ignore_memory_transaction_failures =3D true; in mcimx6ul_evk_machine_init() instead and check if that prevents these (a= nd any future such) failures=2E Best regards, Bernhard > >Signed-off-by: Bin Meng >--- > > hw/arm/fsl-imx6ul=2Ec | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > >diff --git a/hw/arm/fsl-imx6ul=2Ec b/hw/arm/fsl-imx6ul=2Ec >index d6f662efe4=2E=2E74c1a30959 100644 >--- a/hw/arm/fsl-imx6ul=2Ec >+++ b/hw/arm/fsl-imx6ul=2Ec >@@ -210,6 +210,21 @@ static void fsl_imx6ul_realize(DeviceState *dev, Err= or **errp) > create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_= ADDR, > FSL_IMX6UL_A7MPCORE_DAP_SIZE); >=20 >+ /* AIPS bus configuration */ >+ create_unimplemented_device("aips1-config", FSL_IMX6UL_AIPS1_CFG_ADD= R, >+ FSL_IMX6UL_AIPS1_CFG_SIZE); >+ create_unimplemented_device("aips2-config", FSL_IMX6UL_AIPS2_CFG_ADD= R, >+ FSL_IMX6UL_AIPS2_CFG_SIZE); >+ >+ /* SNVS low-power general-purpose registers */ >+ create_unimplemented_device("snvs-lp", FSL_IMX6UL_SNVS_LP_ADDR, >+ FSL_IMX6UL_SNVS_LP_SIZE); >+ >+ /* System counter control */ >+ create_unimplemented_device("sys-counter-control", >+ FSL_IMX6UL_SYS_CNT_CTRL_ADDR, >+ FSL_IMX6UL_SYS_CNT_CTRL_SIZE); >+ > /* > * MMDC > */