From: Xiaoyao Li <xiaoyao.li@intel.com>
To: "Zhao Liu" <zhao1.liu@intel.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Dongli Zhang <dongli.zhang@oracle.com>,
Thomas Huth <thuth@redhat.com>,
qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Like Xu <like.xu.linux@gmail.com>,
Igor Mammedov <imammedo@redhat.com>
Subject: Re: [Regression] Re: [PULL 35/35] qom: reverse order of instance_post_init calls
Date: Wed, 2 Jul 2025 19:42:19 +0800 [thread overview]
Message-ID: <76f8e877-e203-421f-b301-4b321534bd8b@intel.com> (raw)
In-Reply-To: <aGTmFGC9vZB2yEwv@intel.com>
On 7/2/2025 3:56 PM, Zhao Liu wrote:
>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>>> index 0d35e95430fe..bf290262cbfe 100644
>>> --- a/target/i386/cpu.c
>>> +++ b/target/i386/cpu.c
>>> @@ -9044,6 +9044,12 @@ static void x86_cpu_post_initfn(Object *obj)
>>> X86_CONFIDENTIAL_GUEST(current_machine->cgs), (CPU(obj)));
>>> }
>>> #endif
>>> +
>>> + /*
>>> + * Re-apply the "feature[=foo]" from '-cpu' option since they might
>>> + * be overwritten by above
>>> + */
>>> + qdev_prop_set_globals(DEVICE(obj));
>>> }
>>
>> This patch LGTM.
>
> This solution will call qdev_prop_set_globals() twice. My concern is
> that this masks the problem: previous x86 CPU assumptions about the
> order of global property initialization break down...
>
> Per the commit message of Paolo's commit:
>
> "This is incorrect because the leaf class cannot observe property
> values applied by the superclasses; for example, a compat property
> will be set on a device *after* the class's post_init callback has
> run."
After checking the history of why .post_instance_init() was introduced
in the first place: 8231c2dd2203 ("qom: Introduce instance_post_init
hook"). It turns out to be used for qdev_prop_set_globals(), to ensure
global properties being applied after all sub-device specific
instance_init() were called. And I think the order from child to parent
was defined purposely.
And the reverse of Paolo's patch breaks the usage of "-global" than it
won't take effect if the sub-device changes the property in its
post_instance_init() callback.
Back to Paolo's example of "a compat property will be set on a device
*after* the class's post_init callback has run". I think the behavior of
compat property is applied after the class's post_init callback is also
what we want. If reversing the order, then compat prop can be
overwritten by subclass's post_init callback, and doesn't it fail the
purpose of compat prop?
So I think we might revert this patch, and document clearly the reverse
order of .post_instance_init() callback.
> X86 CPUs have the issue (e.g., "vendor" doesn't work) now because
> they - as leaf class, don't care about the property values of
> superclass - the DeviceState. If a property is just for initialization,
> like "vendor", it should be placed in the instance_init() instead of
> instance_post_init().
>
> In addition, if other places handle it similarly, the device's
> post_init seems pointless. :-(
>
> Thanks,
> Zhao
>
next prev parent reply other threads:[~2025-07-02 11:43 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 11:04 [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Paolo Bonzini
2025-05-20 11:04 ` [PULL 01/35] i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 02/35] i386/hvf: Make CPUID_HT supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 03/35] hw/pci-host/gt64120: Fix endianness handling Paolo Bonzini
2025-05-20 11:04 ` [PULL 04/35] hw/pci-host: Remove unused pci_host_data_be_ops Paolo Bonzini
2025-05-20 11:05 ` [PULL 05/35] qapi/misc-target: Rename SGXEPCSection to SgxEpcSection Paolo Bonzini
2025-05-20 11:05 ` [PULL 06/35] qapi/misc-target: Rename SGXInfo to SgxInfo Paolo Bonzini
2025-05-20 11:05 ` [PULL 07/35] qapi/misc-target: Fix the doc related SGXEPCSection Paolo Bonzini
2025-05-20 11:05 ` [PULL 08/35] qapi/misc-target: Fix the doc to distinguish query-sgx and query-sgx-capabilities Paolo Bonzini
2025-05-20 11:05 ` [PULL 09/35] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-05-20 11:05 ` [PULL 10/35] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-05-20 11:05 ` [PULL 11/35] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-05-20 11:05 ` [PULL 12/35] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-05-20 11:05 ` [PULL 13/35] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-05-20 11:05 ` [PULL 14/35] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-05-20 11:05 ` [PULL 15/35] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 16/35] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-05-20 11:05 ` [PULL 17/35] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-05-20 11:05 ` [PULL 18/35] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-05-20 11:05 ` [PULL 19/35] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-05-20 11:05 ` [PULL 20/35] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-05-20 11:05 ` [PULL 21/35] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 22/35] target/riscv: convert profile CPU models " Paolo Bonzini
2025-05-20 11:05 ` [PULL 23/35] target/riscv: convert bare " Paolo Bonzini
2025-05-20 11:05 ` [PULL 24/35] target/riscv: convert dynamic " Paolo Bonzini
2025-05-20 11:05 ` [PULL 25/35] target/riscv: convert SiFive E " Paolo Bonzini
2025-05-20 11:05 ` [PULL 26/35] target/riscv: convert ibex " Paolo Bonzini
2025-05-20 11:05 ` [PULL 27/35] target/riscv: convert SiFive U " Paolo Bonzini
2025-05-20 11:05 ` [PULL 28/35] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-05-20 11:05 ` [PULL 29/35] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-05-20 11:05 ` [PULL 30/35] target/riscv: convert THead C906 to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 31/35] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-05-20 11:05 ` [PULL 32/35] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-05-20 11:05 ` [PULL 33/35] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-05-20 11:05 ` [PULL 34/35] target/riscv: remove .instance_post_init Paolo Bonzini
2025-05-20 11:05 ` [PULL 35/35] qom: reverse order of instance_post_init calls Paolo Bonzini
2025-06-23 16:56 ` [Regression] " Dongli Zhang
2025-06-24 8:57 ` Zhao Liu
2025-06-30 15:22 ` Zhao Liu
2025-07-01 6:50 ` Xiaoyao Li
2025-07-02 6:54 ` Philippe Mathieu-Daudé
2025-07-02 7:56 ` Zhao Liu
2025-07-02 11:42 ` Xiaoyao Li [this message]
2025-07-02 12:12 ` Paolo Bonzini
2025-07-02 13:24 ` Xiaoyao Li
2025-07-02 18:54 ` Paolo Bonzini
2025-07-03 1:03 ` Xiaoyao Li
2025-07-03 3:08 ` Zhao Liu
2025-07-03 3:36 ` Xiaoyao Li
2025-07-03 4:51 ` Paolo Bonzini
2025-07-07 15:41 ` Paolo Bonzini
2025-07-02 12:06 ` Paolo Bonzini
2025-05-21 14:06 ` [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Stefan Hajnoczi
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