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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448eea468sm8310452f8f.26.2026.09.02.11.02.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Sep 2026 11:02:17 -0700 (PDT) Message-ID: <7766d96b-4065-4917-9d7d-094bd6d1f29c@oss.qualcomm.com> Date: Wed, 2 Sep 2026 20:02:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/11] target/arm: Extract halt-to-exec transition out of arm_cpu_exec_halt() Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: Peter Maydell , Richard Henderson Cc: qemu-devel@nongnu.org, Paolo Bonzini , Daniel Henrique Barboza , Pierrick Bouvier References: <20260819145649.23439-1-philmd@oss.qualcomm.com> <20260819145649.23439-7-philmd@oss.qualcomm.com> <44833559-f73d-4b8c-acec-a3e86b98c393@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=YcmNIQRf c=1 sm=1 tr=0 ts=6a9864b1 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=nTIrALyzO7R1oIutnIsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDE1OSBTYWx0ZWRfX/boBUHaW/InO ufm/C6oxN+BVqxhQUkd7abxOAKos66JKgC8C1s1dfI5QfdhxpoCb20Bocp57+kBghZkgrd7BmoU fqNSh45Ag30ABSsZpVwPdEL/Y7DYbBo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDE1OSBTYWx0ZWRfX7Ogz5QccNrM9 t0Gfb7RHvxNxhFBbya4x4jaXe5ymqtlNAb9RtbeFbS7AX1VRmXlZJuxn+1cSBsEKWKDqdGPxvWX V1g/Qw5TUii2BGoEAHZJaNgLP0mg6TFtGwXxcDhnl9ur2RLCgmgfWcDJwLJ2DgM3TZtg9MYyq2c SasJJx5eCm0CkX8F+045AKttB+kGgvkwc3XxGRZNHs83b8Q43PibF6zDQBNrEft78ScbXM5ze8M UDreUmYTTC3HmfXLa1GtLG9UcMnQ0ORb458lYs3sIOefx8dI/bvgXTwfwXImg/gP4EhcH4GD0VZ 2N6yO64yG1vuzDfHoZgClF9Ifam3yAx3Ge8eqPITopNFqonXTG5V0VL2NFwnA6+Rppi/S2mA4vS /MWPtRAbvzpDXwMO8l6H0FDyDBNTEKo8onCY4N37mHSB+JcrI8/foRjmhzzgaWQjvaI2E5lGbGt ay3WSkM+Ht26ul5Uwmw== X-Proofpoint-GUID: s-V-U7BMrt2Y4y6wdhskOXdCP3Ue6GHj X-Proofpoint-ORIG-GUID: s-V-U7BMrt2Y4y6wdhskOXdCP3Ue6GHj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_04,2026-09-02_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020159 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 20/8/26 09:29, Philippe Mathieu-Daudé wrote: > On 2026-08-19 23:40, Peter Maydell wrote: >> On Wed, 19 Aug 2026 at 21:14, Richard Henderson >> wrote: >>> >>> On 8/19/26 07:56, Philippe Mathieu-Daudé wrote: >>>> Refactor the target-specific halt-to-execution transition >>>> logic (disable WFE/WFI timers, clear the halt_reason flag) >>>> into a separate arm_cpu_transition_halt_to_exec() function. >>>> >>>> Signed-off-by: Philippe Mathieu-Daudé >>>> --- >>>>    target/arm/cpu.c | 22 +++++++++++++++------- >>>>    1 file changed, 15 insertions(+), 7 deletions(-) >>>> >>>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c >>>> index 77aa78f00e2..8e9b584559d 100644 >>>> --- a/target/arm/cpu.c >>>> +++ b/target/arm/cpu.c >>>> @@ -870,18 +870,26 @@ static bool >>>> arm_cpu_internal_is_big_endian(CPUState *cs) >>>>    } >>>> >>>>    #ifdef CONFIG_TCG >>>> +static void arm_cpu_transition_halt_to_exec(CPUState *cs) >>>> +{ >>>> +    ARMCPU *cpu = ARM_CPU(cs); >>>> + >>>> +    assert(cpu_has_work(cs)); >>> >>> In reply to patch 11 you suggest removing this. >>> I wonder why you added it in the first place. >> >> Does the accel loop enforce that we hold the BQL when >> arm_cpu_exec_halt() is called? > > For MTTCG: > > mttcg_cpu_thread_fn() > { >   bql_lock(); >   while (1) >     qemu_process_cpu_events(cpu); >     if (cpu_can_run(cpu)) { >       bql_unlock(); >       tcg_cpu_exec(cpu); >         cpu_exec(cpu); >           if (cpu->halted) { >             cpu_has_work_after_processing_async_events(cpu); >               process_async_events(cpu); >                 x86_cpu_process_async_events(); // APIC takes BQL >               cpu_has_work(cpu); >               transition_halt_to_exec(cpu); >                 arm_cpu_transition_halt_to_exec(); // timer_lock >                 x86_cpu_transition_halt_to_exec(); >         ... >       bql_lock(); >       ... > } > > void x86_cpu_process_async_events() > { >     /* (BQL not held) */ >     if (cpu_test_interrupt()) { >         bql_lock(); >         apic_poll_irq(); >           apic_sync_vapic(); >           apic_update_irq(); >             cpu_interrupt(); >         cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); >         bql_unlock(); >     } > } >> If not then the assertion >> is racy, because something might get in and e.g. lower >> an IRQ line so that cpu_has_work() is no longer true >> (which would be fine -- it just means we made the decision >> to wake up and that won vs the incoming interrupt). >> >> On the one hand, if we don't have the BQL in has_work and >> exec_halt then we should be a lot more careful about how >> we code them (e.g. use of the right kind of atomics, and >> there's no way the call to do_interrupt_all() in the x86 >> exec_halt can be safe without the BQL, surely). >> >> On the other hand, if we do have the BQL in exec_halt >> then why is the x86 implementation explicitly taking >> the BQL when it calls apic_poll_irq()? Trying harder, my understanding is apic_poll_irq() only requires the BQL for the apic_update_irq() call, not apic_sync_vapic(). So maybe only apic_sync_vapic() belongs to process_async_events(), leaving apic_update_irq() to transition_halt_to_exec(). Paolo does that sound like going in the good direction?