From: Matthew Auld <matthew.auld@intel.com>
To: Jonathan Cavitt <jonathan.cavitt@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] gen8_ppgtt: Use correct huge page manager for MTL
Date: Tue, 21 Feb 2023 16:07:40 +0000 [thread overview]
Message-ID: <777bfafc-7d98-9d20-a7bf-ecfe5a8fbddb@intel.com> (raw)
In-Reply-To: <0f4df8e9-1cb9-b1a4-284d-67fc75b74c2e@intel.com>
On 21/02/2023 16:06, Matthew Auld wrote:
> On 17/02/2023 19:18, Jonathan Cavitt wrote:
>> MTL currently uses gen8_ppgtt_insert_huge when managing huge pages.
>> This is because
>> MTL reports as not supporting 64K pages, or more accurately, the
>> system that reports
>> whether a platform has 64K pages reports false for MTL. This is only
>> half correct,
>> as the 64K page support reporting system only cares about 64K page
>> support for LMEM,
>> which MTL doesn't have.
>>
>> MTL should be using xehpsdv_ppgtt_insert_huge. However, simply
>> changing over to
>> using that manager doesn't resolve the issue because MTL is expecting
>> the virtual
>> address space for the page table to be flushed after initialization,
>> so we must also
>> add a flush statement there.
>>
>> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Also make sure we use "drm/i915:" prefix for commit title.
>
> Although it looks like the hugepage mock tests are failing with this. I
> assume the mock device just uses some "max" gen version or so, which now
> triggers this path. Any ideas for that?
>
>> ---
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index 4daaa6f55668..9c571185395f 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -570,6 +570,7 @@ xehpsdv_ppgtt_insert_huge(struct
>> i915_address_space *vm,
>> }
>> } while (rem >= page_size && index < max);
>> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
>> vma_res->page_sizes_gtt |= page_size;
>> } while (iter->sg && sg_dma_len(iter->sg));
>> }
>> @@ -707,7 +708,7 @@ static void gen8_ppgtt_insert(struct
>> i915_address_space *vm,
>> struct sgt_dma iter = sgt_dma(vma_res);
>> if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
>> - if (HAS_64K_PAGES(vm->i915))
>> + if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
>> xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter,
>> cache_level, flags);
>> else
>> gen8_ppgtt_insert_huge(vm, vma_res, &iter, cache_level,
>> flags);
next prev parent reply other threads:[~2023-02-21 16:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-17 19:18 [Intel-gfx] [PATCH] gen8_ppgtt: Use correct huge page manager for MTL Jonathan Cavitt
2023-02-17 21:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-02-17 21:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-18 11:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-02-21 16:06 ` [Intel-gfx] [PATCH] " Matthew Auld
2023-02-21 16:07 ` Matthew Auld [this message]
2023-02-21 16:28 ` Cavitt, Jonathan
2023-02-21 16:32 ` Matthew Auld
2023-02-21 17:14 ` Cavitt, Jonathan
2023-02-21 17:46 ` Matthew Auld
2023-02-21 18:34 ` Cavitt, Jonathan
2023-02-22 9:35 ` Matthew Auld
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