All of lore.kernel.org
 help / color / mirror / Atom feed
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
To: Guenter Roeck <linux@roeck-us.net>
Cc: qemu-devel <qemu-devel@nongnu.org>,
	qemu-riscv <qemu-riscv@nongnu.org>,
	 Alistair Francis <alistair23@gmail.com>,
	 Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: Re: [PATCH v3 3/6] hw/riscv: Make FDT optional for MPFS
Date: Mon, 6 Oct 2025 07:14:23 +0200 (CEST)	[thread overview]
Message-ID: <788527663.312.1759727663914.JavaMail.zimbra@embedded-brains.de> (raw)
In-Reply-To: <38528707-3d28-4be8-8b58-60269cb1db1b@roeck-us.net>

Hello Guenter,

thanks for the report. Do you have a Linux image and a Qemu command line so that I can test this?

-- 
embedded brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.huber@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax:   +49-89-18 94 741 - 08

Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/


  reply	other threads:[~2025-10-06  5:14 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-19  6:13 [PATCH v3 0/6] Improve Microchip Polarfire SoC customization Sebastian Huber
2025-03-19  6:13 ` [PATCH v3 1/6] hw/misc: Add MPFS system reset support Sebastian Huber
2025-04-04  1:48   ` Alistair Francis
2025-03-19  6:13 ` [PATCH v3 2/6] hw/riscv: More flexible FDT placement for MPFS Sebastian Huber
2025-03-19  6:13 ` [PATCH v3 3/6] hw/riscv: Make FDT optional " Sebastian Huber
2025-04-04  1:51   ` Alistair Francis
2025-10-04 21:17   ` Guenter Roeck
2025-10-06  5:14     ` Sebastian Huber [this message]
2025-10-06 20:34       ` Guenter Roeck
2025-10-31  2:56         ` Alistair Francis
2025-10-31  7:58           ` Sebastian Huber
2025-10-31 14:17             ` Guenter Roeck
2025-03-19  6:13 ` [PATCH v3 4/6] hw/riscv: Allow direct start of kernel " Sebastian Huber
2025-04-04  2:00   ` Alistair Francis
2025-03-19  6:13 ` [PATCH v3 5/6] hw/riscv: Configurable MPFS CLINT timebase freq Sebastian Huber
2025-04-04  2:11   ` Alistair Francis
2025-03-19  6:13 ` [PATCH v3 6/6] hw/riscv: microchip_pfsoc: Rework documentation Sebastian Huber
2025-04-04  2:25   ` Alistair Francis
2025-04-04  2:33 ` [PATCH v3 0/6] Improve Microchip Polarfire SoC customization Alistair Francis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=788527663.312.1759727663914.JavaMail.zimbra@embedded-brains.de \
    --to=sebastian.huber@embedded-brains.de \
    --cc=alistair23@gmail.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=linux@roeck-us.net \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.