From: Thomas Monjalon <thomas.monjalon@6wind.com>
To: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.ibm.com>
Cc: dev@dpdk.org, "Dumitrescu,
Cristian" <cristian.dumitrescu@intel.com>,
Chao Zhu <chaozhu@linux.vnet.ibm.com>,
"Richardson, Bruce" <bruce.richardson@intel.com>,
"Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
Pradeep <pradeep@us.ibm.com>
Subject: Re: [PATCH v6 9/9] table: align rte table hash structs for cache line size
Date: Thu, 08 Sep 2016 11:36:23 +0200 [thread overview]
Message-ID: <7893708.49gP68faKh@xps13> (raw)
In-Reply-To: <3EB4FA525960D640B5BDFFD6A3D8912647A547BE@IRSMSX108.ger.corp.intel.com>
2016-08-31 17:29, Dumitrescu, Cristian:
> From: Gowrishankar Muthukrishnan
> > rte table hash structs rte_bucket_4_8, rte_bucket_4_16 and
> > rte_bucket_4_32 have
> > to be cache aligned as required by their corresponding hash create functions
> > rte_table_hash_create_key8_lru etc.
>
> Hi Gowrishankar,
>
> My understanding is you are trying to work around the check invoked by the hash table create functions that verifies the size of the bucket header structure is a multiple of the cache line, right?
>
> Given that the size of this structure is 1x, 2x or 3x times 64 bytes, the check passes on IA CPUs (cache line of 64 bytes; explicit alignment to cache line size is not needed in order to make the size of the structure a multiple of cache line), but not on PPC CPUs (cache line of 128 bytes), correct?
>
> I don't think your proposal provides the best way to fix this issue, since your code leads to a considerable increase in the memory consumption used per bucket in most cases:
> - 100% more memory for 8-byte key hash table
> - 0% more for 16-byte key hash table (code does not fix anything, explicit alignment is not needed)
> - 50% more for 32-byte key hash table
>
> I suggest you simply change the check: instead of validating this data structure is a multiple of cache line size, validate it is a multiple of 64 bytes.
Any news please?
The whole series is blocked for this patch.
Should we expect a v7?
next prev parent reply other threads:[~2016-09-08 9:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-16 10:27 [PATCH v6 0/9] enable lpm, acl and other missing libraries in ppc64le Gowrishankar Muthukrishnan
2016-08-16 10:27 ` [PATCH v6 1/9] lpm: add altivec intrinsics for dpdk lpm on ppc_64 Gowrishankar Muthukrishnan
2016-09-07 9:21 ` Bruce Richardson
2016-08-16 10:27 ` [PATCH v6 2/9] acl: add altivec intrinsics for dpdk acl " Gowrishankar Muthukrishnan
2016-08-31 13:08 ` Ananyev, Konstantin
2016-08-16 10:27 ` [PATCH v6 3/9] l3fwd: add altivec support for em_hash_key Gowrishankar Muthukrishnan
2016-08-16 10:27 ` [PATCH v6 4/9] table: enable table library for ppc64le Gowrishankar Muthukrishnan
2016-08-16 10:27 ` [PATCH v6 5/9] sched: enable sched " Gowrishankar Muthukrishnan
2016-08-16 10:27 ` [PATCH v6 6/9] port: enable port " Gowrishankar Muthukrishnan
2016-08-16 10:27 ` [PATCH v6 7/9] pipeline: enable pipeline " Gowrishankar Muthukrishnan
2016-08-16 10:27 ` [PATCH v6 8/9] ip_pipeline: fix lcore mapping for varying SMT threads as in ppc64 Gowrishankar Muthukrishnan
2016-08-31 17:33 ` Dumitrescu, Cristian
2016-08-16 10:27 ` [PATCH v6 9/9] table: align rte table hash structs for cache line size Gowrishankar Muthukrishnan
2016-08-31 17:29 ` Dumitrescu, Cristian
2016-09-08 9:36 ` Thomas Monjalon [this message]
2016-09-08 9:40 ` Dumitrescu, Cristian
2016-09-08 16:52 ` gowrishankar muthukrishnan
2016-08-17 8:48 ` [PATCH v6 0/9] enable lpm, acl and other missing libraries in ppc64le Chao Zhu
2016-08-26 10:55 ` FW: " Chao Zhu
2016-08-26 15:29 ` Thomas Monjalon
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