Re: 2.6.19 timer API changes

[Daniel Laird <danieljlaird@hotmail.com>]

Atsushi Nemoto wrote:
> 
> On Tue, 19 Dec 2006 00:17:24 -0800 (PST), Daniel Laird
> <danieljlaird@hotmail.com> wrote:
>> On the PNX8550 it does not use the CP0 timer but use a different timer
>> (the
>> Custom MIPS core has 3 extra timers) 
> 
> Do you know what this ifndef line mean?
> 
> #ifndef CONFIG_SOC_PNX8550	/* pnx8550 resets to zero */
> 	/* Ack this timer interrupt and set the next one.  */
> 	expirelo += cycles_per_jiffy;
> #endif
> 
> If it means "On PNX8550, writing to COMPARE register resets COUNTER to
> zero", new time.c might be broken for PNX8550.  Could you try this
> patch?
> 
> diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
> index 11aab6d..4eb0741 100644
> --- a/arch/mips/kernel/time.c
> +++ b/arch/mips/kernel/time.c
> @@ -119,7 +119,11 @@ static cycle_t c0_hpt_read(void)
>  /* For use both as a high precision timer and an interrupt source.  */
>  static void __init c0_hpt_timer_init(void)
>  {
> +#ifdef CONFIG_SOC_PNX8550	/* pnx8550 resets to zero */
> +	expirelo = cycles_per_jiffy;
> +#else
>  	expirelo = read_c0_count() + cycles_per_jiffy;
> +#endif
>  	write_c0_compare(expirelo);
>  }
>  
> 
> 
> 
I am just digging out the mips core user manual...  
However I have tried this change you suggested, it still takes a long time
to get past the calibrate delay function (~10seconds).
However after this it seems to run at full speed where as before it used to
run very slow.
So an improvement, I think this does mean the new time.c has broken 8550
support hopefully I can find otu what the core does so it can be fixed.

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