diff for duplicates of <7964326.0VzqzhpvEl@avalon> diff --git a/a/1.txt b/N1/1.txt index 496d39d..5381bd2 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -63,7 +63,7 @@ On Wednesday 26 February 2014 16:33:20 Simon Horman wrote: > + }; > + > + /* Special CPG clocks */ -> + cpg_clocks: cpg_clocks@0xe6150000 { +> + cpg_clocks: cpg_clocks at 0xe6150000 { > + compatible = "renesas,r8a7779-cpg-clocks"; > + reg = <0 0xe6150000 0 0x1000>; @@ -133,7 +133,8 @@ R8A7779_CLK_P>, > + R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 > + R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 > + >; -> + clock-output-names > + "hspi", "tmu00", "tmu01", +> + clock-output-names = +> + "hspi", "tmu00", "tmu01", > + "tmu02", "scif5", "scif4", > + "scif3", "scif2", "scif1", > + "scif0", "i2c3", "i2c2", @@ -159,7 +160,8 @@ R8A7779_CLK_P>, > + R8A7779_CLK_ETHER R8A7779_CLK_SATA > + R8A7779_CLK_PCIE R8A7779_CLK_VIN3 > + >; -> + clock-output-names > + "ehci0", "ohci0", +> + clock-output-names = +> + "ehci0", "ohci0", > + "ehci1", "ohci1", > + "du", "vin2", > + "vin1", "vin0", @@ -180,7 +182,8 @@ R8A7779_CLK_P>, > + R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 > + R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 > + >; -> + clock-output-names > + "sdhi3", "sdhi2", +> + clock-output-names = +> + "sdhi3", "sdhi2", > + "sdhi1", "sdhi0", > + "mmc1", "mmc0"; > + }; diff --git a/a/content_digest b/N1/content_digest index eb7df84..7a3a821 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,8 @@ "ref\01393400016-23433-1-git-send-email-horms+renesas@verge.net.au\0" "ref\01393400016-23433-5-git-send-email-horms+renesas@verge.net.au\0" - "From\0Laurent Pinchart <laurent.pinchart@ideasonboard.com>\0" - "Subject\0Re: [PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks\0" - "Date\0Wed, 26 Feb 2014 14:45:03 +0000\0" + "From\0laurent.pinchart@ideasonboard.com (Laurent Pinchart)\0" + "Subject\0[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks\0" + "Date\0Wed, 26 Feb 2014 15:45:03 +0100\0" "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" @@ -71,7 +71,7 @@ "> +\t\t};\n" "> +\n" "> +\t\t/* Special CPG clocks */\n" - "> +\t\tcpg_clocks: cpg_clocks@0xe6150000 {\n" + "> +\t\tcpg_clocks: cpg_clocks at 0xe6150000 {\n" "> +\t\t\tcompatible = \"renesas,r8a7779-cpg-clocks\";\n" "> +\t\t\treg = <0 0xe6150000 0 0x1000>;\n" "\n" @@ -141,7 +141,8 @@ "> +\t\t\t\tR8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2\n" "> +\t\t\t\tR8A7779_CLK_I2C1 R8A7779_CLK_I2C0\n" "> +\t\t\t>;\n" - "> +\t\t\tclock-output-names > +\t\t\t\t\"hspi\", \"tmu00\", \"tmu01\",\n" + "> +\t\t\tclock-output-names =\n" + "> +\t\t\t\t\"hspi\", \"tmu00\", \"tmu01\",\n" "> +\t\t\t\t\"tmu02\", \"scif5\", \"scif4\",\n" "> +\t\t\t\t\"scif3\", \"scif2\", \"scif1\",\n" "> +\t\t\t\t\"scif0\", \"i2c3\", \"i2c2\",\n" @@ -167,7 +168,8 @@ "> +\t\t\t\tR8A7779_CLK_ETHER R8A7779_CLK_SATA\n" "> +\t\t\t\tR8A7779_CLK_PCIE R8A7779_CLK_VIN3\n" "> +\t\t\t>;\n" - "> +\t\t\tclock-output-names > +\t\t\t\t\"ehci0\", \"ohci0\",\n" + "> +\t\t\tclock-output-names =\n" + "> +\t\t\t\t\"ehci0\", \"ohci0\",\n" "> +\t\t\t\t\"ehci1\", \"ohci1\",\n" "> +\t\t\t\t\"du\", \"vin2\",\n" "> +\t\t\t\t\"vin1\", \"vin0\",\n" @@ -188,7 +190,8 @@ "> +\t\t\t\tR8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0\n" "> +\t\t\t\tR8A7779_CLK_MMC1 R8A7779_CLK_MMC0\n" "> +\t\t\t>;\n" - "> +\t\t\tclock-output-names > +\t\t\t\t\"sdhi3\", \"sdhi2\",\n" + "> +\t\t\tclock-output-names =\n" + "> +\t\t\t\t\"sdhi3\", \"sdhi2\",\n" "> +\t\t\t\t\"sdhi1\", \"sdhi0\",\n" "> +\t\t\t\t\"mmc1\", \"mmc0\";\n" "> +\t\t};\n" @@ -200,4 +203,4 @@ "\n" Laurent Pinchart -cbd5d41592c480032c08036f04a1589709b87a127847faa0d108b0c7a480947e +be14b51735d80fc2336ac5460922b8bb2eeb9e9bb7820e5ebde626f89a6b1e46
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