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Received: from SJ1PR12MB6051.namprd12.prod.outlook.com (2603:10b6:a03:48a::18) by CH8PR12MB9741.namprd12.prod.outlook.com (2603:10b6:610:27a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.10; Fri, 11 Sep 2026 10:33:15 +0000 Received: from SJ1PR12MB6051.namprd12.prod.outlook.com ([fe80::96e1:b300:7b78:d3a9]) by SJ1PR12MB6051.namprd12.prod.outlook.com ([fe80::96e1:b300:7b78:d3a9%6]) with mapi id 15.21.0382.014; Fri, 11 Sep 2026 10:33:15 +0000 Message-ID: <79b104a2-a76d-415b-b98c-6833d8cd298f@nvidia.com> Date: Fri, 11 Sep 2026 11:33:09 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] mtd: spi-nor: Fix quad-enable for flashes with QER bit in SR1 To: Miquel Raynal , Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260911-perso-fix-spi-nor-qe-mxic-v1-1-fd6d91416a2a@bootlin.com> Content-Language: en-US From: Jon Hunter In-Reply-To: <20260911-perso-fix-spi-nor-qe-mxic-v1-1-fd6d91416a2a@bootlin.com> X-ClientProxiedBy: PA7P264CA0297.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:370::7) To SJ1PR12MB6051.namprd12.prod.outlook.com (2603:10b6:a03:48a::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PR12MB6051:EE_|CH8PR12MB9741:EE_ X-MS-Office365-Filtering-Correlation-Id: bbc3b377-4942-450a-6aeb-08df0ff0162d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|7416014|376014|366016|10067099003|11063799006|56012099006|22082099003|18002099003; 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charset="us-ascii"; Format="flowed" Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On 11/09/2026 09:55, Miquel Raynal wrote: > Some flashes (eg. from Macronix) do set BFPT_DWORD15_QER_SR1_BIT6, which > means they do not have an SR2 to read from/write to. The new generic QE > helper was supposed to accommodate this situation but in the last version > that got merged, parts of that specific handling has been moved to a > more contained location, swp.c (which needed most of the extra code), > yet the Macronix case has been forgotten about in that generic QE > handling helper. Booting with such flashes will always fail probing. > > Fix the situation by making sure we do not attempt to read SR2 if the QE > bit is in SR1. > > Reported-by: Jon Hunter > Closes: https://lore.kernel.org/linux-mtd/178876719232.3543902.14451625037676421254.b4-ty@b4/T/#m5bc4ba6776436f2870ced0eb5789d229037ad840 > Fixes: 63489002d397 ("mtd: spi-nor: Refactor Read Status/Write Status support") > Signed-off-by: Miquel Raynal > --- > drivers/mtd/spi-nor/core.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index e2b6efafdd8d..ac909dfb9657 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -985,7 +985,10 @@ static int spi_nor_generic_quad_enable(struct spi_nor *nor) > if (!qe_mask[0] && !qe_mask[1]) > return 0; > > - ret = spi_nor_read_sr1_and_sr2(nor, sr); > + if (qe_mask[0]) > + ret = spi_nor_read_sr1(nor, sr); > + else > + ret = spi_nor_read_sr1_and_sr2(nor, sr); > if (ret) > return ret; I know that there is still some discussion going on about this patch, but FWIW this does fix the issue I was seeing. Thanks Jon -- nvpublic ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/