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Wed, 24 Jun 2026 13:00:44 -0700 (PDT) Received: from strix.localnet ([197.250.227.156]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49264011d5fsm17039315e9.1.2026.06.24.13.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jun 2026 13:00:41 -0700 (PDT) From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH RFC v4 10/12] reset: zte: Add a zx297520v3 reset driver Date: Wed, 24 Jun 2026 23:00:04 +0300 Message-ID: <7_XKp5ZWTJeJfxJieymOJA@gmail.com> In-Reply-To: <90c4f50eb23dec06497d46f9c0f522a6b90a918b.camel@pengutronix.de> References: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com> <20260616-zx29clk-v4-10-ca994bd22e9d@gmail.com> <90c4f50eb23dec06497d46f9c0f522a6b90a918b.camel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextParthVt_moD_RiKok0jux0DKSA"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextParthVt_moD_RiKok0jux0DKSA Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= Subject: Re: [PATCH RFC v4 10/12] reset: zte: Add a zx297520v3 reset driver Date: Wed, 24 Jun 2026 23:00:04 +0300 Message-ID: <7_XKp5ZWTJeJfxJieymOJA@gmail.com> In-Reply-To: <90c4f50eb23dec06497d46f9c0f522a6b90a918b.camel@pengutronix.de> MIME-Version: 1.0 Hi Philipp, Am Donnerstag, 18. Juni 2026, 12:24:26 Ostafrikanische Zeit schrieb Philipp Zabel: > > + [ZX297520V3_UART0_RESET] = { .reg = 0x78, .mask = BIT(6) | BIT(7) > > }, > Is this a single reset line controlled by two bits (do you know what > they are)? Or might these actually be two different reset controls that > are just always set together? I suppose I could expose both bits as separate reset controls in the binding. The lower bit is usually the one that actually resets the device, while the higher one works similarly to PCLK - it disconnects the device from the bus, if asserted. Depending on the device it may or may not leave any residual effect behind after deassert. The stumbling block is the dwc2 USB driver. It only takes one reset, so I'd have to add another one (or abuse the dwc2-ecc reset) and presumably add a PHY driver for the 3rd reset or add a dwc2-phy reset. The AMBA bus already takes an array of resets, so the pl011 UARTs are fine either way. For stmmac I need a glue driver for other reasons anyway. the dwc,mmc2 controller on this board seems to have only one reset, so no need to extend the driver here. --nextParthVt_moD_RiKok0jux0DKSA Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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