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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4858ac2b4cdsm5738768f8f.16.2026.09.04.09.11.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Sep 2026 09:11:40 -0700 (PDT) Message-ID: <7a6ef890-a630-46b3-aedf-a687fec487cc@oss.qualcomm.com> Date: Fri, 4 Sep 2026 18:11:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 00/24] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot To: Bin Meng , QEMU Cc: Alistair Francis , Alistair Francis , Bin Meng , Chao Liu , Conor Dooley , Daniel Henrique Barboza , "Edgar E. Iglesias" , Fabiano Rosas , Laurent Vivier , Liu Zhiwei , Markus Armbruster , Palmer Dabbelt , Paolo Bonzini , Peter Maydell , Pierrick Bouvier , Sebastian Huber , Thomas Huth , Weiwei Li , qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org References: <20260904155758.3833179-1-bin.meng@processmission.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= Content-Language: en-US In-Reply-To: <20260904155758.3833179-1-bin.meng@processmission.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA0MDE0NyBTYWx0ZWRfX+M+2wLJf/Joa yy03r4tEj7ArcvYkFRYRIfzNH5wbb/tO6MF9izzrSdhbdEsxAmbN+dhZfgjvxI871RBxFFdvXl/ 6a9TFdGK0AiBsyMSxnevx7M/86ULvEj194jtUHJ2sBSv7x7kOjUx/VNiER+O51wkKxEMMpXxorP jV/ym8JCc2aZzJ2gGVrQCd/zgLS6DdLH36rnQhvSb7VVxrv5i49Bg3Omy95xq2QIcsRY7Fldvjc cVLPy9aWCFrZqtB2QAyxGr8OCKja66XD5vWAzreWDb8sCDt8xQuYVCY8dHRZ8UPcL0e8OF5zIjs x1W2h8uvUWT6kD4t14hJ5xgPZVaRV/QAWrfls/JjW6n8SuWPwo0hkaHrB4/UOxtQ8nXd7qO6Dog EgjnB12ivb58/kGoJN4VWjBZr9I+1nXEUSrxGRRUMe3tMyRJaCS87FGreHN0BW9UFXEoq6mwRHh dvw+EkBoa+/ARX6f/UA== X-Proofpoint-GUID: albAhsLJdlmRRIB4ojT-9LZ6uqv8Uqej X-Proofpoint-ORIG-GUID: albAhsLJdlmRRIB4ojT-9LZ6uqv8Uqej X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA0MDE0NyBTYWx0ZWRfX9xwFALXnheEp WeCjYTS8WQR+6T74ibH+WlX7/YQYjC+Q9DNqzEZ8VXV1Wv3fufkeLP/NP5TBWUFBrg0ifodzG6Q emycpxdS2O4Z53UhCoXLqxysZ39o8F8= X-Authority-Analysis: v=2.4 cv=Ibi3n2qa c=1 sm=1 tr=0 ts=6a9aedbe cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=fSYeKqFsUNyXvTew9nkA:9 a=QEXdDO2ut3YA:10 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-04_04,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 bulkscore=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609040147 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/9/26 17:57, Bin Meng wrote: > Bin Meng (23): > hw/riscv: pfsoc: Correct the L2LIM maximum mapped size > hw/riscv: pfsoc: Map the L2 zero device window > hw/misc: pfsoc: Support DDR training with newer HSS > hw/misc: pfsoc: Model L2 cache controller registers > hw/riscv: pfsoc: Couple L2CC to L2-LIM > tests/qtest: Add PolarFire SoC L2CC coverage > hw/sd: sdhci: Run ADMA independently of MMIO > hw/sd: sd: Keep high-capacity memory blocks at 512 bytes > hw/sd: cadence: Add 64-bit system bus property FYI I tagged this series (in particular the SD/HCI patches) to review but won't be able to until Sept 21. Not a blocker although if Alistair think the series is ready. > hw/riscv: pfsoc: Enable 64-bit SDHCI system bus support > hw/misc: pfsoc: Model PolarFire SoC serial number service > hw/rtc: Add PolarFire SoC RTC model > hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit > tests/qtest: Add PolarFire SoC RTC coverage > hw/misc: pfsoc: Honor PolarFire service notification requests > hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases > hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB > hw/riscv: pfsoc: Fix Icicle Kit hart count at five > docs/system/riscv: Document Icicle Kit HSS boot > docs/system/riscv: pfsoc: Document CLINT topology for direct Linux > boot > tests/functional/riscv64: Add Icicle Kit firmware boot test > MAINTAINERS: Add PolarFire SoC Icicle Kit maintainer > MAINTAINERS: Move Conor Dooley to PolarFire SoC reviewer