Re: [PATCH 2/8] x86/IDT: Collect IDT related content idt.h

[Jan Beulich <jbeulich@suse.com>]

On 26.02.2025 18:15, Andrew Cooper wrote:
> On 25/02/2025 8:27 am, Jan Beulich wrote:
>> On 24.02.2025 17:05, Andrew Cooper wrote:
>>> --- /dev/null
>>> +++ b/xen/arch/x86/include/asm/idt.h
>>> @@ -0,0 +1,125 @@
>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>>> +#ifndef X86_ASM_IDT_H
>>> +#define X86_ASM_IDT_H
>>> +
>>> +#include <xen/bug.h>
>>> +#include <xen/types.h>
>>> +
>>> +#include <asm/x86-defns.h>
>>> +
>>> +#define IST_NONE 0
>>> +#define IST_MCE  1
>>> +#define IST_NMI  2
>>> +#define IST_DB   3
>>> +#define IST_DF   4
>>> +#define IST_MAX  4
>>> +
>>> +typedef union {
>>> +    struct {
>>> +        uint64_t a, b;
>>> +    };
>>> +    struct {
>>> +        uint16_t addr0;
>>> +        uint16_t cs;
>>> +        uint8_t  ist; /* :3, 5 bits rsvd, but this yields far better code. */
>>> +        uint8_t  type:4, s:1, dpl:2, p:1;
>>> +        uint16_t addr1;
>>> +        uint32_t addr2;
>>> +        /* 32 bits rsvd. */
>>> +    };
>>> +} idt_entry_t;
>>> +
>>> +#define IDT_ENTRIES 256
>>> +extern idt_entry_t idt_table[];
>>> +extern idt_entry_t *idt_tables[];
>>> +
>>> +/*
>>> + * Set the Interrupt Stack Table used by a particular IDT entry.  Typically
>>> + * used on a live IDT, so volatile to disuade clever optimisations.
>>> + */
>>> +static inline void set_ist(volatile idt_entry_t *idt, unsigned int ist)
>>> +{
>>> +    /* IST is a 3 bit field, 32 bits into the IDT entry. */
>>> +    ASSERT(ist <= IST_MAX);
>>> +
>>> +    idt->ist = ist;
>>> +}
>>> +
>>> +static inline void enable_each_ist(idt_entry_t *idt)
>>> +{
>>> +    set_ist(&idt[X86_EXC_DF],  IST_DF);
>>> +    set_ist(&idt[X86_EXC_NMI], IST_NMI);
>>> +    set_ist(&idt[X86_EXC_MC],  IST_MCE);
>>> +    set_ist(&idt[X86_EXC_DB],  IST_DB);
>>> +}
>>> +
>>> +static inline void disable_each_ist(idt_entry_t *idt)
>>> +{
>>> +    set_ist(&idt[X86_EXC_DF],  IST_NONE);
>>> +    set_ist(&idt[X86_EXC_NMI], IST_NONE);
>>> +    set_ist(&idt[X86_EXC_MC],  IST_NONE);
>>> +    set_ist(&idt[X86_EXC_DB],  IST_NONE);
>>> +}
>>> +
>>> +/*
>>> + * Write the lower 64 bits of an IDT Entry. This relies on the upper 32
>>> + * bits of the address not changing, which is a safe assumption as all
>>> + * functions we are likely to load will live inside the 1GB
>>> + * code/data/bss address range.
>>> + */
>>> +static inline void _write_gate_lower(volatile idt_entry_t *gate,
>>> +                                     const idt_entry_t *new)
>>> +{
>>> +    ASSERT(gate->b == new->b);
>>> +    gate->a = new->a;
>>> +}
>> Would this better move down a few lines, immediately ahead of its two
>> use sites?
>>
>>> +#define _set_gate(gate_addr,type,dpl,addr)               \
>> Moving this is questionable, as gates aren't limited to the IDT (in
>> principle; yes, we don't use call gates ourselves). However, as you
>> move it, my minimal request would be to add the missing blanks here.
> 
> _set_gate() doesn't survive to the end of the series, which also fixes
> the position of _write_gate_lower().

Hmm, okay:
Acked-by: Jan Beulich <jbeulich@suse.com>

Jan