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envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Hey, On 9/11/2026 4:22 PM, Christian wrote: > > Hi, > >> The risc v privileged specification requires hinval.vvma, hinval.gvma, >> sfence.w.inval and sfence.inval.ir should raise a virtual instruction >> exception when executed in the vu-mode. This patch add the check to >> raise the virtual instruction exception when is in the vu-mode. >> >> changes in v2: >> - Remove the wrong `return true;` from macro >> >> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621 >> >> Signed-off-by: Christian S. Lima >> --- >> target/riscv/tcg/insn_trans/trans_svinval.c.inc | 3 +++ >> target/riscv/tcg/insn_trans/trans_xthead.c.inc | 12 +++++++----- >> 2 files changed, 10 insertions(+), 5 deletions(-) >> >> diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc b/target/riscv/tcg/insn_trans/trans_svinval.c.inc >> index 4614c1489c..5b1172672e 100644 >> --- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc >> +++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc >> @@ -25,6 +25,9 @@ >> /* Test if priv level is M or S. */ >> #define REQUIRE_PRIV_MS(ctx) do { \ >> if (ctx->priv == PRV_U) { \ >> + if (ctx->virt_enabled) { \ >> + ctx->virt_inst_excp = true \ > > I missed a `;` here and below, should I resend a v3? Yes, please send a v3. I believe the patch as is will not compile. Thanks, Daniel >> + } \ >> return false; \ >> } \ >> } while (0) >> diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/insn_trans/trans_xthead.c.inc >> index f4e3051000..4bf6594747 100644 >> --- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc >> +++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc >> @@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) >> #define REQUIRE_PRIV_MSU(ctx) >> >> /* Test if priv level is M or S. */ >> -#define REQUIRE_PRIV_MS(ctx) \ >> -do { \ >> - if (ctx->priv == PRV_U) { \ >> - return false; \ >> - } \ >> +#define REQUIRE_PRIV_MS(ctx) do { \ >> + if (ctx->priv == PRV_U) { \ >> + if (ctx->virt_enabled) { \ >> + ctx->virt_inst_excp = true \ >> + } \ >> + return false; \ >> + } \ >> } while (0) >> >> #define NOP_PRIVCHECK(insn, extcheck, privcheck) \ >> -- >> 2.55.0 >> >> > > Thanks, > Christian