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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760ab363sm598975666b.114.2025.01.27.07.12.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Jan 2025 07:12:07 -0800 (PST) Message-ID: <7e118726-b22b-4c7b-9966-07c3b1ff709c@oss.qualcomm.com> Date: Mon, 27 Jan 2025 16:12:05 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] cpufreq: qcom-nvmem: Enable cpufreq for ipq5424 To: Sricharan R , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, ilia.lin@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20250127093128.2611247-1-quic_srichara@quicinc.com> <20250127093128.2611247-4-quic_srichara@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250127093128.2611247-4-quic_srichara@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ba0__87Ur2DQr_e3NIfdyM0Pucs5cj5v X-Proofpoint-ORIG-GUID: ba0__87Ur2DQr_e3NIfdyM0Pucs5cj5v X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 phishscore=0 suspectscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 On 27.01.2025 10:31 AM, Sricharan R wrote: > From: Md Sadre Alam > > IPQ5424 have different OPPs available for the CPU based on > SoC variant. This can be determined through use of an eFuse > register present in the silicon. > > Added support for ipq5424 on nvmem driver which helps to > determine OPPs at runtime based on the eFuse register which > has the CPU frequency limits. opp-supported-hw dt binding > can be used to indicate the available OPPs for each limit. > > nvmem driver also creates the "cpufreq-dt" platform_device after > passing the version matching data to the OPP framework so that the > cpufreq-dt handles the actual cpufreq implementation. > > Signed-off-by: Md Sadre Alam > Signed-off-by: Sricharan Ramabadhran > --- > drivers/cpufreq/cpufreq-dt-platdev.c | 1 + > drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c > index 9c198bd4f7e9..4045bc3ce805 100644 > --- a/drivers/cpufreq/cpufreq-dt-platdev.c > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c > @@ -187,6 +187,7 @@ static const struct of_device_id blocklist[] __initconst = { > { .compatible = "ti,am62p5", }, > > { .compatible = "qcom,ipq5332", }, > + { .compatible = "qcom,ipq5424", }, > { .compatible = "qcom,ipq6018", }, > { .compatible = "qcom,ipq8064", }, > { .compatible = "qcom,ipq8074", }, > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c > index 3a8ed723a23e..102f7f1b031c 100644 > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c > @@ -200,6 +200,10 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, > case QCOM_ID_IPQ9574: > drv->versions = 1 << (unsigned int)(*speedbin); > break; > + case QCOM_ID_IPQ5424: > + case QCOM_ID_IPQ5404: > + drv->versions = (*speedbin != 0x3b) ? BIT(0) : BIT(1); Perhaps: drv->versions = (*speedbin == 0x3b) ? BIT(1) : BIT(0); But ultimately both work: Reviewed-by: Konrad Dybcio Konrad