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Mon, 17 Nov 2025 07:18:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CF.mail.protection.outlook.com (10.167.240.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Mon, 17 Nov 2025 07:18:15 +0000 Received: from [172.20.96.43] (unknown [172.20.96.43]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id B43AB40A5BD5; Mon, 17 Nov 2025 15:18:14 +0800 (CST) Message-ID: <7f1ce6c2-df20-48d6-99c7-411346b526a5@cixtech.com> Date: Mon, 17 Nov 2025 15:18:14 +0800 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] dma: arm-dma350: add support for shared interrupt mode To: Krzysztof Kozlowski , peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org References: <20251117015943.2858-1-jun.guo@cixtech.com> <20251117015943.2858-3-jun.guo@cixtech.com> Content-Language: en-US From: Jun Guo In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 07:18:15.6767 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0f5ff8e-7ff8-4109-f9ac-08de25a979ec X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CF.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB5651 On 11/17/2025 2:13 PM, Krzysztof Kozlowski wrote: > On 17/11/2025 02:59, Jun Guo wrote: >> - The arm dma350 controller's hardware implementation varies: some > That's not a list. Look at git history to learn how to write expected > commit messages. > Thank you. I will incorporate your feedback in the next version.>> designs dedicate a separate interrupt line for each channel, while >> others have all channels sharing a single interrupt.This patch adds >> support for the hardware design where all DMA channels share a >> single interrupt. >> >> Signed-off-by: Jun Guo >> --- >> drivers/dma/ar > > >> @@ -526,7 +593,7 @@ static void d350_free_chan_resources(struct dma_chan *chan) >> static int d350_probe(struct platform_device *pdev) >> { >> struct device *dev = &pdev->dev; >> - struct d350 *dmac; >> + struct d350 *dmac = NULL; >> void __iomem *base; >> u32 reg; >> int ret, nchan, dw, aw, r, p; >> @@ -556,6 +623,7 @@ static int d350_probe(struct platform_device *pdev) >> return -ENOMEM; >> >> dmac->nchan = nchan; >> + dmac->base = base; >> >> reg = readl_relaxed(base + DMAINFO + DMA_BUILDCFG1); >> dmac->nreq = FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg); >> @@ -582,6 +650,26 @@ static int d350_probe(struct platform_device *pdev) >> dmac->dma.device_issue_pending = d350_issue_pending; >> INIT_LIST_HEAD(&dmac->dma.channels); >> >> + /* Cix Sky1 has a common host IRQ for all its channels. */ >> + if (of_device_is_compatible(pdev->dev.of_node, "cix,sky1-dma-350")) { > No, see further > >> + int host_irq = platform_get_irq(pdev, 0); >> + >> + if (host_irq < 0) >> + return dev_err_probe(dev, host_irq, >> + "Failed to get IRQ\n"); >> + >> + ret = devm_request_irq(&pdev->dev, host_irq, d350_global_irq, >> + IRQF_SHARED, DRIVER_NAME, dmac); >> + if (ret) >> + return dev_err_probe( >> + dev, ret, >> + "Failed to request the combined IRQ %d\n", >> + host_irq); >> + >> + /* Combined Non-Secure Channel Interrupt Enable */ >> + writel_relaxed(INTREN_ANYCHINTR_EN, dmac->base + DMANSECCTRL); >> + } >> + >> /* Would be nice to have per-channel caps for this... */ >> memset = true; >> for (int i = 0; i < nchan; i++) { >> @@ -595,10 +683,16 @@ static int d350_probe(struct platform_device *pdev) >> dev_warn(dev, "No command link support on channel %d\n", i); >> continue; >> } >> - dch->irq = platform_get_irq(pdev, i); >> - if (dch->irq < 0) >> - return dev_err_probe(dev, dch->irq, >> - "Failed to get IRQ for channel %d\n", i); >> + >> + if (!of_device_is_compatible(pdev->dev.of_node, >> + "cix,sky1-dma-350")) { > No, use driver match data for that. Sprinkling compatibles everywhere > does not scale. > > Also, this is in contrary with the binding, which did not say your > device has no interrupts. Ok, I'll rework the patch based on your feedback. Best regards, Jun