Re: [PATCH 2/3] drm/i915/dp: Ignore the sink's DSC max FRL rate without a PCON DSC encoder

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 6/10/2026 11:14 PM, Alexander Kaplan wrote:
> intel_dp_hdmi_sink_max_frl() limits the sink's max FRL rate by its
> DSC max FRL rate whenever the sink supports DSC 1.2.
> However, the DSC max FRL rate (HF-VSDB DSC_Max_FRL_Rate) only applies
> to compressed video transport, which requires a DSC 1.2 encoder in
> the PCON (configured via intel_dp_pcon_dsc_configure()).
> Without such an encoder the HDMI link always carries uncompressed
> video, for which the regular Max_FRL_Rate is the correct limit.
>
> Applying the DSC limit unconditionally trains the FRL link at a lower
> rate than both the PCON and the sink support.
> E.g. an LG OLED G4 (Max_FRL_Rate 48 Gbps, DSC_Max_FRL_Rate 24 Gbps)
> behind a Synaptics VMM7100 PCON (PCON max FRL bw 48 Gbps, no DSC
> encoder):
>
>    Sink max rate from EDID = 24 Gbps
>    FRL trained with : 24 Gbps
>
> while Windows/macOS train the same hardware at 40/48 Gbps.
> The too low FRL rate needlessly constrains the formats available to
> the sink.
>
> Only apply the sink's DSC max FRL rate if the PCON has a DSC 1.2
> encoder, matching the gate in intel_dp_pcon_dsc_configure().
> PCONs with a DSC encoder keep the current conservative behavior,
> since the link is trained once and compressed transport may be used
> for any subsequent mode.
> With this the setup above trains at 48 Gbps.
>
> Tested on PTL (xe) with the above PCON/sink combo.
>
> Fixes: 10fec80b48c5 ("drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding")
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Alexander Kaplan <alexander.kaplan@sms-medipool.de>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 13cfccf60490..2831b274d88a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4254,7 +4254,14 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
>   	rate_per_lane = info->hdmi.max_frl_rate_per_lane;
>   	max_frl_rate = max_lanes * rate_per_lane;
>   
> -	if (info->hdmi.dsc_cap.v_1p2) {
> +	/*
> +	 * The sink's DSC max FRL rate only applies to compressed video
> +	 * transport, which requires a DSC 1.2 encoder in the PCON. Without
> +	 * one the HDMI link always carries uncompressed video, for which
> +	 * the regular max FRL rate is the limit.
> +	 */
> +	if (drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) &&
> +	    info->hdmi.dsc_cap.v_1p2) {

Yes, this is very much needed.

This condition could be factored into a separate helper, but that can be 
a separate patch.

Patch looks good to me as it is.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


>   		max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;
>   		dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;
>   		if (max_dsc_lanes && dsc_rate_per_lane)