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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-ad51aee5ca8sm1391664a12.43.2025.02.06.09.47.27 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Feb 2025 09:47:27 -0800 (PST) Message-ID: <7f6fc0ae-6cdd-4996-b411-762019efb003@linaro.org> Date: Thu, 6 Feb 2025 09:47:26 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift() To: qemu-devel@nongnu.org References: <20250206173258.36624-1-philmd@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250206173258.36624-1-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/6/25 09:32, Philippe Mathieu-Daudé wrote: > We only support 32-bit TriCore architecture. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/tricore/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/tricore/translate.c b/target/tricore/translate.c > index 6819b776686..c5b783b6a70 100644 > --- a/target/tricore/translate.c > +++ b/target/tricore/translate.c > @@ -5936,7 +5936,7 @@ static void decode_rr_logical_shift(DisasContext *ctx) > break; > case OPC2_32_RR_CLO: > tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); > - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); > + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32); > break; > case OPC2_32_RR_CLO_H: > gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); > @@ -5948,7 +5948,7 @@ static void decode_rr_logical_shift(DisasContext *ctx) > gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); > break; > case OPC2_32_RR_CLZ: > - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); > + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32); > break; > case OPC2_32_RR_CLZ_H: > gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); Leave it alone unless you swap /_tl/_i32/ ? r~