From mboxrd@z Thu Jan 1 00:00:00 1970 From: Leo Liu Subject: Re: [PATCH 3/5] drm/amdgpu: enable system interrupt for jrbc Date: Thu, 19 Jul 2018 14:13:50 -0400 Message-ID: <7ff97103-bd17-3011-103d-a4e2e77099a6@amd.com> References: <1531946355-17488-1-git-send-email-boyuan.zhang@amd.com> <1531946355-17488-3-git-send-email-boyuan.zhang@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1531946355-17488-3-git-send-email-boyuan.zhang-5C7GfCeVMHo@public.gmane.org> Content-Language: en-GB List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: boyuan.zhang-5C7GfCeVMHo@public.gmane.org, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org CgpPbiAwNy8xOC8yMDE4IDA0OjM5IFBNLCBib3l1YW4uemhhbmdAYW1kLmNvbSB3cm90ZToKPiBG cm9tOiBCb3l1YW4gWmhhbmcgPGJveXVhbi56aGFuZ0BhbWQuY29tPgo+Cj4gRW5hYmxlIHN5c3Rl bSBpbnRlcnJ1cHQgZm9yIGpyYmMgZHVyaW5nIGVuZ2luZSBzdGFydGluZyB0aW1lLgo+Cj4gU2ln bmVkLW9mZi1ieTogQm95dWFuIFpoYW5nIDxib3l1YW4uemhhbmdAYW1kLmNvbT4KPiAtLS0KPiAg IGRyaXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1L3Zjbl92MV8wLmMgfCA4ICsrKysrKystCj4gICAx IGZpbGUgY2hhbmdlZCwgNyBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9uKC0pCj4KPiBkaWZmIC0t Z2l0IGEvZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvdmNuX3YxXzAuYyBiL2RyaXZlcnMvZ3B1 L2RybS9hbWQvYW1kZ3B1L3Zjbl92MV8wLmMKPiBpbmRleCA0ZmNjYjIxLi4yMmMxNTg4IDEwMDY0 NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1L3Zjbl92MV8wLmMKPiArKysgYi9k cml2ZXJzL2dwdS9kcm0vYW1kL2FtZGdwdS92Y25fdjFfMC5jCj4gQEAgLTU5NSw2ICs1OTUsNyBA QCBzdGF0aWMgaW50IHZjbl92MV8wX3N0YXJ0KHN0cnVjdCBhbWRncHVfZGV2aWNlICphZGV2KQo+ ICAgCXN0cnVjdCBhbWRncHVfcmluZyAqcmluZyA9ICZhZGV2LT52Y24ucmluZ19kZWM7Cj4gICAJ dWludDMyX3QgcmJfYnVmc3osIHRtcDsKPiAgIAl1aW50MzJfdCBsbWlfc3dhcF9jbnRsOwo+ICsJ dWludDMyX3QgcmVnX3RlbXA7Cj4gICAJaW50IGksIGosIHI7Cj4gICAKPiAgIAkvKiBkaXNhYmxl IGJ5dGUgc3dhcHBpbmcgKi8KPiBAQCAtNzAwLDYgKzcwMSwxMSBAQCBzdGF0aWMgaW50IHZjbl92 MV8wX3N0YXJ0KHN0cnVjdCBhbWRncHVfZGV2aWNlICphZGV2KQo+ICAgCQkoVVZEX01BU1RJTlRf RU5fX1ZDUFVfRU5fTUFTS3xVVkRfTUFTVElOVF9FTl9fU1lTX0VOX01BU0spLAo+ICAgCQl+KFVW RF9NQVNUSU5UX0VOX19WQ1BVX0VOX01BU0t8VVZEX01BU1RJTlRfRU5fX1NZU19FTl9NQVNLKSk7 Cj4gICAKPiArCS8qIGVuYWJsZSBzeXN0ZW0gaW50ZXJydXB0IGZvciBKUkJDKi8KPiArCXJlZ190 ZW1wID0gUlJFRzMyKFNPQzE1X1JFR19PRkZTRVQoVVZELCAwLCBtbVVWRF9TWVNfSU5UX0VOKSk7 Cj4gKwlyZWdfdGVtcCB8PSBVVkRfU1lTX0lOVF9FTl9fVVZEX0pSQkNfRU5fTUFTSzsKPiArCVdS RUczMihTT0MxNV9SRUdfT0ZGU0VUKFVWRCwgMCwgbW1VVkRfU1lTX0lOVF9FTiksIHJlZ190ZW1w KTsKCkhlcmUgeW91IGNvdWxkIHVzZSBiZWxvdyBpbnN0ZWFkLgpXUkVHMzJfUChTT0MxNV9SRUdf T0ZGU0VUKFVWRCwgMCwgbW1VVkRfU1lTX0lOVF9FTiksIFVWRF9TWVNfSU5UX0VOX19VVkRfSlJC Q19FTl9NQVNLLAoJflVWRF9TWVNfSU5UX0VOX19VVkRfSlJCQ19FTl9NQVNLKTsKCkV0aGVyIHdh eSwgdGhlIHdob2xlIHNlcmllcyBhcmUKQWNrZWQtYnk6IExlbyBMaXUgPGxlby5saXVAYW1kLmNv bT4KCgoKPiArCj4gICAJLyogY2xlYXIgdGhlIGJpdCA0IG9mIFZDTl9TVEFUVVMgKi8KPiAgIAlX UkVHMzJfUChTT0MxNV9SRUdfT0ZGU0VUKFVWRCwgMCwgbW1VVkRfU1RBVFVTKSwgMCwKPiAgIAkJ CX4oMiA8PCBVVkRfU1RBVFVTX19WQ1BVX1JFUE9SVF9fU0hJRlQpKTsKPiBAQCAtMTc1NCw3ICsx NzYwLDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBhbWRncHVfaXJxX3NyY19mdW5jcyB2Y25fdjFf MF9pcnFfZnVuY3MgPSB7Cj4gICAKPiAgIHN0YXRpYyB2b2lkIHZjbl92MV8wX3NldF9pcnFfZnVu Y3Moc3RydWN0IGFtZGdwdV9kZXZpY2UgKmFkZXYpCj4gICB7Cj4gLQlhZGV2LT52Y24uaXJxLm51 bV90eXBlcyA9IGFkZXYtPnZjbi5udW1fZW5jX3JpbmdzICsgMTsKPiArCWFkZXYtPnZjbi5pcnEu bnVtX3R5cGVzID0gYWRldi0+dmNuLm51bV9lbmNfcmluZ3MgKyAyOwo+ICAgCWFkZXYtPnZjbi5p cnEuZnVuY3MgPSAmdmNuX3YxXzBfaXJxX2Z1bmNzOwo+ICAgfQo+ICAgCgpfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwphbWQtZ2Z4IG1haWxpbmcgbGlzdAph bWQtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9y Zy9tYWlsbWFuL2xpc3RpbmZvL2FtZC1nZngK