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[71.197.186.152]) by smtp.gmail.com with ESMTPSA id g22sm515509pgk.85.2019.12.09.14.25.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Dec 2019 14:25:57 -0800 (PST) From: Kevin Hilman To: Martin Blumenstingl , p.zabel@pengutronix.de, linux-amlogic@lists.infradead.org Subject: Re: [PATCH] dt-bindings: reset: meson8b: fix duplicate reset IDs In-Reply-To: <20191130185337.1757000-1-martin.blumenstingl@googlemail.com> References: <20191130185337.1757000-1-martin.blumenstingl@googlemail.com> Date: Mon, 09 Dec 2019 14:25:57 -0800 Message-ID: <7h5ziprv9m.fsf@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191209_142558_757378_2CD43F69 X-CRM114-Status: UNSURE ( 5.74 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Martin Blumenstingl writes: > According to the public S805 datasheet the RESET2 register uses the > following bits for the PIC_DC, PSC and NAND reset lines: > - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3) > - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4) > - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4) > > Update the reset IDs of these three reset lines so they don't conflict > with PIC_DC and map to the actual hardware reset lines. > > Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller") > Signed-off-by: Martin Blumenstingl Queued as a fix for v5.5-rc, Thanks, Kevin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2D47C04E30 for ; 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[71.197.186.152]) by smtp.gmail.com with ESMTPSA id g22sm515509pgk.85.2019.12.09.14.25.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Dec 2019 14:25:57 -0800 (PST) From: Kevin Hilman To: Martin Blumenstingl , p.zabel@pengutronix.de, linux-amlogic@lists.infradead.org Subject: Re: [PATCH] dt-bindings: reset: meson8b: fix duplicate reset IDs In-Reply-To: <20191130185337.1757000-1-martin.blumenstingl@googlemail.com> References: <20191130185337.1757000-1-martin.blumenstingl@googlemail.com> Date: Mon, 09 Dec 2019 14:25:57 -0800 Message-ID: <7h5ziprv9m.fsf@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191209_142558_921180_D0BB9444 X-CRM114-Status: UNSURE ( 7.29 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Martin Blumenstingl writes: > According to the public S805 datasheet the RESET2 register uses the > following bits for the PIC_DC, PSC and NAND reset lines: > - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3) > - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4) > - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4) > > Update the reset IDs of these three reset lines so they don't conflict > with PIC_DC and map to the actual hardware reset lines. > > Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller") > Signed-off-by: Martin Blumenstingl Queued as a fix for v5.5-rc, Thanks, Kevin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90D8CC43603 for ; Mon, 9 Dec 2019 22:26:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 64F392071E for ; Mon, 9 Dec 2019 22:26:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="NSH9ULh/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726718AbfLIW0B (ORCPT ); Mon, 9 Dec 2019 17:26:01 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:34123 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726156AbfLIW0A (ORCPT ); Mon, 9 Dec 2019 17:26:00 -0500 Received: by mail-pf1-f193.google.com with SMTP id n13so7968948pff.1 for ; Mon, 09 Dec 2019 14:25:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:in-reply-to:references:date:message-id :mime-version; bh=e8vzmB2zQOVicf37JYB7f5dUsZ9PAEbPEnqlneCb8hk=; b=NSH9ULh/1hAOLuPMNPJfxklHlE41CsUwmWn/AlWHF+NXzPTPqa461LIDyAeuIK1ZkC jcvFyZM62M3TyE35p9IkhgrSTYl8uWlVlLUlyqR/zuwW4GTq75XDmk4xOazIivi0fjRQ HFStxYtDHWNEI+Hi/mOViXqpYWFULyktYYG0zvxkLbmQRhlWfpW8XO+VfQ0ml1j/lvz0 OXmR1i8k6mKWWm8qHSSNqiiyPxT2sWUaaBZY7l5mRmphES0IKelAqESY+DkgQA28PRT1 qvTzEDzU9U9VU7mP4ridDIou1QERo9IFl+safi1TbqdJMwfr07By6LDNeDRrT6sR0EIb PNXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:in-reply-to:references:date :message-id:mime-version; bh=e8vzmB2zQOVicf37JYB7f5dUsZ9PAEbPEnqlneCb8hk=; b=n8N0P88fWr/FTk29aeWS0N9w9o6eXvv2mysxMS2s7kNojjI3D6NgcSj6U/iDqu+kq0 /2oZK0ywmW83agLjNSUwKC402ru3e3xLnAmuvIFaJzO60aHAe3KbAFMS754KvxcxZc2H yQj/ZBUyikNGZubiOqCb4RoJm50RXycME8QFfx/Kzh5x9+Z8FK/llgiXvQzMNVtYEjW7 UsWNT72h7sa4kH8EGbp3v9vT7hnsJuj63VOcdUJSvDNAL7QKfqcVrgloo94fGDTbcKGq 5MSMlR9f0FZVELwtYEq5HlY50YwTaT2uRC6YEy1oKFViyLoZAc6mBzTz7uEs7ynzQt5g /R9g== X-Gm-Message-State: APjAAAV5ShSR2BTaTdNL3lthjuL5qXZKy0vWCJri3CoP1qg9YML0LcWR qy1fGEg350fzEXUbW6gFeD+ykw== X-Google-Smtp-Source: APXvYqywvsTO2z1jHZUpDVc2D7xS1pwfKfSChZ6K2XJIA8v7tS/ZhIBV/gXtqeqzdKHsR1Wdvopmsg== X-Received: by 2002:a62:3706:: with SMTP id e6mr32484589pfa.31.1575930358173; Mon, 09 Dec 2019 14:25:58 -0800 (PST) Received: from localhost (c-71-197-186-152.hsd1.wa.comcast.net. [71.197.186.152]) by smtp.gmail.com with ESMTPSA id g22sm515509pgk.85.2019.12.09.14.25.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Dec 2019 14:25:57 -0800 (PST) From: Kevin Hilman To: Martin Blumenstingl , p.zabel@pengutronix.de, linux-amlogic@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, narmstrong@baylibre.com, Martin Blumenstingl Subject: Re: [PATCH] dt-bindings: reset: meson8b: fix duplicate reset IDs In-Reply-To: <20191130185337.1757000-1-martin.blumenstingl@googlemail.com> References: <20191130185337.1757000-1-martin.blumenstingl@googlemail.com> Date: Mon, 09 Dec 2019 14:25:57 -0800 Message-ID: <7h5ziprv9m.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Martin Blumenstingl writes: > According to the public S805 datasheet the RESET2 register uses the > following bits for the PIC_DC, PSC and NAND reset lines: > - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3) > - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4) > - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4) > > Update the reset IDs of these three reset lines so they don't conflict > with PIC_DC and map to the actual hardware reset lines. > > Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller") > Signed-off-by: Martin Blumenstingl Queued as a fix for v5.5-rc, Thanks, Kevin