From mboxrd@z Thu Jan 1 00:00:00 1970 From: khilman@baylibre.com (Kevin Hilman) Date: Fri, 07 Oct 2016 07:43:48 -0700 Subject: [PATCH] ARM64: dts: meson-gx: Add missing L2 cache node In-Reply-To: <1475675630-31514-1-git-send-email-narmstrong@baylibre.com> (Neil Armstrong's message of "Wed, 5 Oct 2016 15:53:50 +0200") References: <1475675630-31514-1-git-send-email-narmstrong@baylibre.com> Message-ID: <7h7f9kfcd7.fsf@baylibre.com> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org Neil Armstrong writes: > In order to remove the boot warning : > [ 2.290933] Unable to detect cache hierarchy from DT for CPU 0 > And add missing L2 cache hierarchy information, add a simple l2 cache node > and reference it from the A53 cpu nodes. > > Signed-off-by: Neil Armstrong Applied to v4.10/dt64. Kevin From mboxrd@z Thu Jan 1 00:00:00 1970 From: khilman@baylibre.com (Kevin Hilman) Date: Fri, 07 Oct 2016 07:43:48 -0700 Subject: [PATCH] ARM64: dts: meson-gx: Add missing L2 cache node In-Reply-To: <1475675630-31514-1-git-send-email-narmstrong@baylibre.com> (Neil Armstrong's message of "Wed, 5 Oct 2016 15:53:50 +0200") References: <1475675630-31514-1-git-send-email-narmstrong@baylibre.com> Message-ID: <7h7f9kfcd7.fsf@baylibre.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Neil Armstrong writes: > In order to remove the boot warning : > [ 2.290933] Unable to detect cache hierarchy from DT for CPU 0 > And add missing L2 cache hierarchy information, add a simple l2 cache node > and reference it from the A53 cpu nodes. > > Signed-off-by: Neil Armstrong Applied to v4.10/dt64. Kevin From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kevin Hilman Subject: Re: [PATCH] ARM64: dts: meson-gx: Add missing L2 cache node Date: Fri, 07 Oct 2016 07:43:48 -0700 Message-ID: <7h7f9kfcd7.fsf@baylibre.com> References: <1475675630-31514-1-git-send-email-narmstrong@baylibre.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1475675630-31514-1-git-send-email-narmstrong@baylibre.com> (Neil Armstrong's message of "Wed, 5 Oct 2016 15:53:50 +0200") List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Neil Armstrong Cc: carlo@caione.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org Neil Armstrong writes: > In order to remove the boot warning : > [ 2.290933] Unable to detect cache hierarchy from DT for CPU 0 > And add missing L2 cache hierarchy information, add a simple l2 cache node > and reference it from the A53 cpu nodes. > > Signed-off-by: Neil Armstrong Applied to v4.10/dt64. Kevin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756857AbcJGOpi (ORCPT ); Fri, 7 Oct 2016 10:45:38 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]:33541 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752289AbcJGOoj (ORCPT ); Fri, 7 Oct 2016 10:44:39 -0400 From: Kevin Hilman To: Neil Armstrong Cc: carlo@caione.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH] ARM64: dts: meson-gx: Add missing L2 cache node Organization: BayLibre References: <1475675630-31514-1-git-send-email-narmstrong@baylibre.com> Date: Fri, 07 Oct 2016 07:43:48 -0700 In-Reply-To: <1475675630-31514-1-git-send-email-narmstrong@baylibre.com> (Neil Armstrong's message of "Wed, 5 Oct 2016 15:53:50 +0200") Message-ID: <7h7f9kfcd7.fsf@baylibre.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Neil Armstrong writes: > In order to remove the boot warning : > [ 2.290933] Unable to detect cache hierarchy from DT for CPU 0 > And add missing L2 cache hierarchy information, add a simple l2 cache node > and reference it from the A53 cpu nodes. > > Signed-off-by: Neil Armstrong Applied to v4.10/dt64. Kevin