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From: khilman@baylibre.com (Kevin Hilman)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b
Date: Fri, 27 Apr 2018 12:08:10 -0700	[thread overview]
Message-ID: <7hd0yk1n8l.fsf@baylibre.com> (raw)
In-Reply-To: <20180422104502.2942-1-martin.blumenstingl@googlemail.com> (Martin Blumenstingl's message of "Sun, 22 Apr 2018 12:45:00 +0200")

Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:

> Meson8 uses Cortex-A9 cores and Meson8b uses Cortex-A5 cores. As most
> Cortex-A5/A9 implementation these Amlogic SoCs also come with a
> built-in PMU for counting cpu and cache events like cache misses and
> hits.

Applied to v4.18/dt,

Thanks,

Kevin

      parent reply	other threads:[~2018-04-27 19:08 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-22 10:45 [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b Martin Blumenstingl
2018-04-22 10:45 ` [PATCH 1/2] ARM: dts: meson8: add the cortex-a9-pmu compatible PMU Martin Blumenstingl
2018-04-22 10:45 ` [PATCH 2/2] ARM: dts: meson8b: add the cortex-a5-pmu " Martin Blumenstingl
2018-04-27 19:08 ` Kevin Hilman [this message]

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