From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kevin Hilman Subject: Re: [PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated Date: Wed, 10 Dec 2014 09:35:31 -0800 Message-ID: <7hlhmfo1b0.fsf@deeprootsystems.com> References: <1417788934-23447-1-git-send-email-k.kozlowski@samsung.com> <1418129982.19339.6.camel@AMDC1943> <5486F69B.6020005@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Received: from mail-pa0-f41.google.com ([209.85.220.41]:43919 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756089AbaLJRff convert rfc822-to-8bit (ORCPT ); Wed, 10 Dec 2014 12:35:35 -0500 Received: by mail-pa0-f41.google.com with SMTP id rd3so3217472pab.14 for ; Wed, 10 Dec 2014 09:35:34 -0800 (PST) In-Reply-To: <5486F69B.6020005@samsung.com> (Sylwester Nawrocki's message of "Tue, 09 Dec 2014 14:18:19 +0100") Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: Sylwester Nawrocki Cc: Krzysztof Kozlowski , Mike Turquette , Tomasz Figa , Stephen Boyd , Kukjin Kim , linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Javier Martinez Canillas , Kyungmin Park , Marek Szyprowski , Bartlomiej Zolnierkiewicz Sylwester Nawrocki writes: > On 09/12/14 13:59, Krzysztof Kozlowski wrote: >> On pi=C4=85, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote: >>> > Audio subsystem clocks are located in separate block. On Exynos 5= 420 if >>> > clock for this block (from main clock domain) 'mau_epll' is gated= then >>> > any read or write to audss registers will block. >>> >=20 >>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/= Pit >>> > after introducing runtime PM to pl330 DMA driver. After that comm= it the >>> > 'mau_epll' was gated, because the "amba" clock was disabled and t= here >>> > were no more users of mau_epll. >>> >=20 >>> > The system hang on one of steps: >>> > 1. Disabling unused clocks from audss block. >>> > 2. During audss GPIO setup (just before probing i2s0 because >>> > samsung_pinmux_setup() tried to access memory from audss block= which was >>> > gated. >>> >=20 >>> > Add a workaround for this by enabling the 'mau_epll' clock in pro= be. >>> >=20 >>> > Signed-off-by: Krzysztof Kozlowski >>> > --- >>> > drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++= ++++++++- >>> > 1 file changed, 28 insertions(+), 1 deletion(-) >> >> Sorry for pinging so quick but merge window is open and it looks lik= e >> booting Exynos542x boards will be broken (because pl330 will no long= er >> hold adma clock enabled so whole audss domain will be gated). >>=20 >> This is a non-intrusive workaround for that issue, as wanted by >> Sylwester: >> https://lkml.org/lkml/2014/12/5/223 >>=20 >> Any comments on this? > > The patch looks OK to me, it would be good though if someone else > has confirmed it fixes the bug. I don't have any clock patches queued > at the moment. Perhaps you could apply it directly, Mike ? I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig. Tested-by: Kevin Hilman Kevin From mboxrd@z Thu Jan 1 00:00:00 1970 From: khilman@kernel.org (Kevin Hilman) Date: Wed, 10 Dec 2014 09:35:31 -0800 Subject: [PATCH] clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated In-Reply-To: <5486F69B.6020005@samsung.com> (Sylwester Nawrocki's message of "Tue, 09 Dec 2014 14:18:19 +0100") References: <1417788934-23447-1-git-send-email-k.kozlowski@samsung.com> <1418129982.19339.6.camel@AMDC1943> <5486F69B.6020005@samsung.com> Message-ID: <7hlhmfo1b0.fsf@deeprootsystems.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Sylwester Nawrocki writes: > On 09/12/14 13:59, Krzysztof Kozlowski wrote: >> On pi?, 2014-12-05 at 15:15 +0100, Krzysztof Kozlowski wrote: >>> > Audio subsystem clocks are located in separate block. On Exynos 5420 if >>> > clock for this block (from main clock domain) 'mau_epll' is gated then >>> > any read or write to audss registers will block. >>> > >>> > This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit >>> > after introducing runtime PM to pl330 DMA driver. After that commit the >>> > 'mau_epll' was gated, because the "amba" clock was disabled and there >>> > were no more users of mau_epll. >>> > >>> > The system hang on one of steps: >>> > 1. Disabling unused clocks from audss block. >>> > 2. During audss GPIO setup (just before probing i2s0 because >>> > samsung_pinmux_setup() tried to access memory from audss block which was >>> > gated. >>> > >>> > Add a workaround for this by enabling the 'mau_epll' clock in probe. >>> > >>> > Signed-off-by: Krzysztof Kozlowski >>> > --- >>> > drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++- >>> > 1 file changed, 28 insertions(+), 1 deletion(-) >> >> Sorry for pinging so quick but merge window is open and it looks like >> booting Exynos542x boards will be broken (because pl330 will no longer >> hold adma clock enabled so whole audss domain will be gated). >> >> This is a non-intrusive workaround for that issue, as wanted by >> Sylwester: >> https://lkml.org/lkml/2014/12/5/223 >> >> Any comments on this? > > The patch looks OK to me, it would be good though if someone else > has confirmed it fixes the bug. I don't have any clock patches queued > at the moment. Perhaps you could apply it directly, Mike ? I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig. Tested-by: Kevin Hilman Kevin