diff for duplicates of <8060f38c3db6d2f6e1cb7eb6d6bbc199d289aa7d.camel@mediatek.com> diff --git a/a/1.txt b/N1/1.txt index e70bd11..1fbdd21 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -126,4 +126,8 @@ CK > +#define CTS_REQ_EN BIT(1) > +#define CTS_SW_SEL (1) > + -> +> +-- +linux-phy mailing list +linux-phy@lists.infradead.org +https://lists.infradead.org/mailman/listinfo/linux-phy diff --git a/a/content_digest b/N1/content_digest index fb4c6bf..bbfe0ad 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -155,6 +155,10 @@ "> +#define CTS_REQ_EN BIT(1)\n" "> +#define CTS_SW_SEL (1)\n" "> +\n" - > + "> \n" + "-- \n" + "linux-phy mailing list\n" + "linux-phy@lists.infradead.org\n" + https://lists.infradead.org/mailman/listinfo/linux-phy -c6784b066721a5b0f97af1e9c99d5e381f1dab71feabcafca366a83ff6d1785b +6efad253cb1170650f4b14458f7610e47c7ba0ed7a29714d89604b4e17c9eaa9
diff --git a/a/1.txt b/N2/1.txt index e70bd11..54f2efc 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -126,4 +126,8 @@ CK > +#define CTS_REQ_EN BIT(1) > +#define CTS_SW_SEL (1) > + -> +> +_______________________________________________ +linux-arm-kernel mailing list +linux-arm-kernel@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/a/content_digest b/N2/content_digest index fb4c6bf..5485cf7 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -155,6 +155,10 @@ "> +#define CTS_REQ_EN BIT(1)\n" "> +#define CTS_SW_SEL (1)\n" "> +\n" - > + "> \n" + "_______________________________________________\n" + "linux-arm-kernel mailing list\n" + "linux-arm-kernel@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -c6784b066721a5b0f97af1e9c99d5e381f1dab71feabcafca366a83ff6d1785b +52020b5685416fd9af06d45083a9d8ca3e96281be402bb10c7d072945572a0fd
diff --git a/N3/1.bin b/N3/1.bin new file mode 100644 index 0000000..2883e81 --- /dev/null +++ b/N3/1.bin @@ -0,0 +1,144 @@ +<pre> +Hi, Guillaume: + +On Fri, 2022-11-04 at 15:09 +0100, Guillaume Ranquet wrote: +> Adds hdmi and hdmi-ddc support for v2 IP. +>  +> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> +> --- +>  drivers/gpu/drm/mediatek/Makefile           |    2 + +>  drivers/gpu/drm/mediatek/mtk_hdmi_common.c  |   14 + +>  drivers/gpu/drm/mediatek/mtk_hdmi_common.h  |    1 + +>  drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c  |  367 +++++++ +>  drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h |  309 ++++++ +>  drivers/gpu/drm/mediatek/mtk_hdmi_v2.c      | 1379 +> +++++++++++++++++++++++++++ +>  drivers/gpu/drm/mediatek/mtk_hdmi_v2.h      |   29 + +>  7 files changed, 2101 insertions(+) +>  +>  + +[snip] + +> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h +> b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h +> new file mode 100644 +> index 000000000000..f4c3652f4eab +> --- /dev/null +> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h +> @@ -0,0 +1,309 @@ +> +/* SPDX-License-Identifier: GPL-2.0 */ +> +/* +> + * Copyright (c) 2021 MediaTek Inc. +> + * Copyright (c) 2021 BayLibre, SAS +> + */ +> + +> +#ifndef _MTK_HDMI_REGS_H +> +#define _MTK_HDMI_REGS_H +> + +> +#define AIF_HEADER GENMASK(19, 0) +> +#define AIF_PKT00 GENMASK(31, 0) +> +#define AIF_PKT01 (23, 0) +> +#define AIF_PKT02 (31, 0) +> +#define AIF_PKT03 (23, 0) + +Useless, drop it. + +> + +> +#define AIP_CTRL BIT(10) + +I think this is + +#define AIP_CTRL 0x400 + + +> +#define AIP_CTS_SVAL 0x408 +> +#define AIP_DOWNSAMPLE_CTRL 0x41C +> +#define AIP_I2S_CHST0 0x414 +> +#define AIP_I2S_CHST1 0x418 +> +#define AIP_I2S_CTRL 0x410 +> +#define AIP_N_VAL 0x404 +> +#define AIP_SPDIF_CTRL 0x40C +> +#define AIP_TPI_CTRL 0x428 +> +#define AIP_TXCTRL 0x424 +> + +> +#define AUD_DIS (0x0) +> +#define AUD_DIS_WR (0x0) +> +#define AUD_EN BIT(2) +> +#define AUD_EN_WR BIT(18) +> +#define AUD_ERR_THRESH GENMASK(29, 24) +> +#define AUD_IN_EN BIT(8) +> +#define AUD_MUTE_DIS (0x0) +> +#define AUD_MUTE_FIFO_EN BIT(5) +> +#define AUD_PACKET_DROP BIT(6) +> +#define AUD_RPT_DIS (0x0) +> +#define AUD_RPT_EN BIT(2) +> +#define AUD_SEL_OWRT BIT(9) + +I would like to put the bitwise definition with double word definition +together. You could reference [1]. + +[1]  +https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_rdma.c?h=v6.2-rc1 + + +Regards, +CK + +> + +> +#define AVI_DIS (0) +> +#define AVI_DIS_WR (0) +> +#define AVI_EN (0x1) +> +#define AVI_EN_WR BIT(16) +> +#define AVI_HEADER GENMASK(23, 0) +> +#define AVI_PKT00 GENMASK(31, 0) +> +#define AVI_PKT01 GENMASK(23, 0) +> +#define AVI_PKT02 GENMASK(31, 0) +> +#define AVI_PKT03 GENMASK(23, 0) +> +#define AVI_PKT04 GENMASK(31, 0) +> +#define AVI_PKT05 GENMASK(23, 0) +> +#define AVI_RPT_DIS (0x0) +> +#define AVI_RPT_EN (0x1) +> + +> +#define C422_C420_CONFIG_BYPASS BIT(5) +> +#define C422_C420_CONFIG_ENABLE BIT(4) +> +#define C422_C420_CONFIG_OUT_CB_OR_CR BIT(6) +> +#define C444_C422_CONFIG_ENABLE (0x1) +> + +> +#define CBIT_ORDER_SAME BIT(13) +> + +> +#define CEA_AUD_EN BIT(9) +> +#define CEA_AVI_EN BIT(11) +> +#define CEA_CP_EN BIT(6) +> +#define CEA_SPD_EN BIT(10) +> + +> +#define CLEAR_FIFO 0x9 +> + +> +#define CLOCK_SCL 0xA +> + +> +#define CP_CLR_MUTE_EN BIT(1) +> +#define CP_EN BIT(5) +> +#define CP_EN_WR BIT(21) +> +#define CP_RPT_EN BIT(5) +> +#define CP_SET_MUTE_DIS (0) +> +#define CP_SET_MUTE_EN (1) +> + +> +#define CTS_CAL_N4 BIT(23) +> +#define CTS_REQ_EN BIT(1) +> +#define CTS_SW_SEL (1) +> + +>  + +</pre><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice ******************** +The information contained in this e-mail message (including any +attachments) may be confidential, proprietary, privileged, or otherwise +exempt from disclosure under applicable laws. It is intended to be +conveyed only to the designated recipient(s). Any use, dissemination, +distribution, printing, retaining or copying of this e-mail (including its +attachments) by unintended recipient(s) is strictly prohibited and may +be unlawful. If you are not an intended recipient of this e-mail, or believe +that you have received this e-mail in error, please notify the sender +immediately (by replying to this e-mail), delete any and all copies of +this e-mail (including any attachments) from your system, and do not +disclose the content of this e-mail to any other person. Thank you! +</pre><!--}--> diff --git a/N3/2.hdr b/N3/2.hdr new file mode 100644 index 0000000..45d76fc --- /dev/null +++ b/N3/2.hdr @@ -0,0 +1,3 @@ +Content-Type: text/plain; + charset="utf-8" +Content-Transfer-Encoding: base64 diff --git a/a/1.txt b/N3/2.txt similarity index 100% rename from a/1.txt rename to N3/2.txt diff --git a/a/content_digest b/N3/content_digest index fb4c6bf..9845bc6 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -15,17 +15,163 @@ krzysztof.kozlowski+dt@linaro.org <krzysztof.kozlowski+dt@linaro.org> vkoul@kernel.org <vkoul@kernel.org> " matthias.bgg@gmail.com <matthias.bgg@gmail.com>\0" - "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" - linux-mediatek@lists.infradead.org <linux-mediatek@lists.infradead.org> + "Cc\0devicetree@vger.kernel.org <devicetree@vger.kernel.org>" + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org> " Mac Shen (\346\262\210\344\277\212) <Mac.Shen@mediatek.com>" - devicetree@vger.kernel.org <devicetree@vger.kernel.org> - krzysztof.kozlowski@linaro.org <krzysztof.kozlowski@linaro.org> " Stuart Lee (\346\235\216\347\277\260) <Stuart.Lee@mediatek.com>" - dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org> - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + krzysztof.kozlowski@linaro.org <krzysztof.kozlowski@linaro.org> + linux-mediatek@lists.infradead.org <linux-mediatek@lists.infradead.org> linux-phy@lists.infradead.org <linux-phy@lists.infradead.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> " angelogioacchino.delregno@collabora.com <angelogioacchino.delregno@collabora.com>\0" - "\00:1\0" + "\01:1\0" + "b\0" + "<pre>\r\n" + "Hi, Guillaume:\r\n" + "\r\n" + "On Fri, 2022-11-04 at 15:09 +0100, Guillaume Ranquet wrote:\r\n" + "> Adds hdmi and hdmi-ddc support for v2 IP.\r\n" + "> \r\n" + "> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>\r\n" + "> ---\r\n" + ">  drivers/gpu/drm/mediatek/Makefile           |    2 +\r\n" + ">  drivers/gpu/drm/mediatek/mtk_hdmi_common.c  |   14 +\r\n" + ">  drivers/gpu/drm/mediatek/mtk_hdmi_common.h  |    1 +\r\n" + ">  drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c  |  367 +++++++\r\n" + ">  drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h |  309 ++++++\r\n" + ">  drivers/gpu/drm/mediatek/mtk_hdmi_v2.c      | 1379\r\n" + "> +++++++++++++++++++++++++++\r\n" + ">  drivers/gpu/drm/mediatek/mtk_hdmi_v2.h      |   29 +\r\n" + ">  7 files changed, 2101 insertions(+)\r\n" + "> \r\n" + "> \r\n" + "\r\n" + "[snip]\r\n" + "\r\n" + "> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h\r\n" + "> b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h\r\n" + "> new file mode 100644\r\n" + "> index 000000000000..f4c3652f4eab\r\n" + "> --- /dev/null\r\n" + "> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h\r\n" + "> @@ -0,0 +1,309 @@\r\n" + "> +/* SPDX-License-Identifier: GPL-2.0 */\r\n" + "> +/*\r\n" + "> + * Copyright (c) 2021 MediaTek Inc.\r\n" + "> + * Copyright (c) 2021 BayLibre, SAS\r\n" + "> + */\r\n" + "> +\r\n" + "> +#ifndef _MTK_HDMI_REGS_H\r\n" + "> +#define _MTK_HDMI_REGS_H\r\n" + "> +\r\n" + "> +#define AIF_HEADER GENMASK(19, 0)\r\n" + "> +#define AIF_PKT00 GENMASK(31, 0)\r\n" + "> +#define AIF_PKT01 (23, 0)\r\n" + "> +#define AIF_PKT02 (31, 0)\r\n" + "> +#define AIF_PKT03 (23, 0)\r\n" + "\r\n" + "Useless, drop it.\r\n" + "\r\n" + "> +\r\n" + "> +#define AIP_CTRL BIT(10)\r\n" + "\r\n" + "I think this is\r\n" + "\r\n" + "#define AIP_CTRL 0x400\r\n" + "\r\n" + "\r\n" + "> +#define AIP_CTS_SVAL 0x408\r\n" + "> +#define AIP_DOWNSAMPLE_CTRL 0x41C\r\n" + "> +#define AIP_I2S_CHST0 0x414\r\n" + "> +#define AIP_I2S_CHST1 0x418\r\n" + "> +#define AIP_I2S_CTRL 0x410\r\n" + "> +#define AIP_N_VAL 0x404\r\n" + "> +#define AIP_SPDIF_CTRL 0x40C\r\n" + "> +#define AIP_TPI_CTRL 0x428\r\n" + "> +#define AIP_TXCTRL 0x424\r\n" + "> +\r\n" + "> +#define AUD_DIS (0x0)\r\n" + "> +#define AUD_DIS_WR (0x0)\r\n" + "> +#define AUD_EN BIT(2)\r\n" + "> +#define AUD_EN_WR BIT(18)\r\n" + "> +#define AUD_ERR_THRESH GENMASK(29, 24)\r\n" + "> +#define AUD_IN_EN BIT(8)\r\n" + "> +#define AUD_MUTE_DIS (0x0)\r\n" + "> +#define AUD_MUTE_FIFO_EN BIT(5)\r\n" + "> +#define AUD_PACKET_DROP BIT(6)\r\n" + "> +#define AUD_RPT_DIS (0x0)\r\n" + "> +#define AUD_RPT_EN BIT(2)\r\n" + "> +#define AUD_SEL_OWRT BIT(9)\r\n" + "\r\n" + "I would like to put the bitwise definition with double word definition\r\n" + "together. You could reference [1].\r\n" + "\r\n" + "[1] \r\n" + "https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_rdma.c?h=v6.2-rc1\r\n" + "\r\n" + "\r\n" + "Regards,\r\n" + "CK\r\n" + "\r\n" + "> +\r\n" + "> +#define AVI_DIS (0)\r\n" + "> +#define AVI_DIS_WR (0)\r\n" + "> +#define AVI_EN (0x1)\r\n" + "> +#define AVI_EN_WR BIT(16)\r\n" + "> +#define AVI_HEADER GENMASK(23, 0)\r\n" + "> +#define AVI_PKT00 GENMASK(31, 0)\r\n" + "> +#define AVI_PKT01 GENMASK(23, 0)\r\n" + "> +#define AVI_PKT02 GENMASK(31, 0)\r\n" + "> +#define AVI_PKT03 GENMASK(23, 0)\r\n" + "> +#define AVI_PKT04 GENMASK(31, 0)\r\n" + "> +#define AVI_PKT05 GENMASK(23, 0)\r\n" + "> +#define AVI_RPT_DIS (0x0)\r\n" + "> +#define AVI_RPT_EN (0x1)\r\n" + "> +\r\n" + "> +#define C422_C420_CONFIG_BYPASS BIT(5)\r\n" + "> +#define C422_C420_CONFIG_ENABLE BIT(4)\r\n" + "> +#define C422_C420_CONFIG_OUT_CB_OR_CR BIT(6)\r\n" + "> +#define C444_C422_CONFIG_ENABLE (0x1)\r\n" + "> +\r\n" + "> +#define CBIT_ORDER_SAME BIT(13)\r\n" + "> +\r\n" + "> +#define CEA_AUD_EN BIT(9)\r\n" + "> +#define CEA_AVI_EN BIT(11)\r\n" + "> +#define CEA_CP_EN BIT(6)\r\n" + "> +#define CEA_SPD_EN BIT(10)\r\n" + "> +\r\n" + "> +#define CLEAR_FIFO 0x9\r\n" + "> +\r\n" + "> +#define CLOCK_SCL 0xA\r\n" + "> +\r\n" + "> +#define CP_CLR_MUTE_EN BIT(1)\r\n" + "> +#define CP_EN BIT(5)\r\n" + "> +#define CP_EN_WR BIT(21)\r\n" + "> +#define CP_RPT_EN BIT(5)\r\n" + "> +#define CP_SET_MUTE_DIS (0)\r\n" + "> +#define CP_SET_MUTE_EN (1)\r\n" + "> +\r\n" + "> +#define CTS_CAL_N4 BIT(23)\r\n" + "> +#define CTS_REQ_EN BIT(1)\r\n" + "> +#define CTS_SW_SEL (1)\r\n" + "> +\r\n" + "> \r\n" + "\r\n" + "</pre><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice ********************\r\n" + "The information contained in this e-mail message (including any \r\n" + "attachments) may be confidential, proprietary, privileged, or otherwise\r\n" + "exempt from disclosure under applicable laws. It is intended to be \r\n" + "conveyed only to the designated recipient(s). Any use, dissemination, \r\n" + "distribution, printing, retaining or copying of this e-mail (including its \r\n" + "attachments) by unintended recipient(s) is strictly prohibited and may \r\n" + "be unlawful. If you are not an intended recipient of this e-mail, or believe \r\n" + "that you have received this e-mail in error, please notify the sender \r\n" + "immediately (by replying to this e-mail), delete any and all copies of \r\n" + "this e-mail (including any attachments) from your system, and do not\r\n" + "disclose the content of this e-mail to any other person. Thank you!\r\n" + </pre><!--}--> + "\01:2\0" "b\0" "Hi, Guillaume:\n" "\n" @@ -157,4 +303,4 @@ "> +\n" > -c6784b066721a5b0f97af1e9c99d5e381f1dab71feabcafca366a83ff6d1785b +83832ba49da486e8b14f1119cf9d80a5b4ba22c7f42ade4dca315279a5f12509
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