From: Rodrigo Siqueira Jordao <Rodrigo.Siqueira@amd.com>
To: Aurabindo Pillai <aurabindo.pillai@amd.com>,
amd-gfx@lists.freedesktop.org
Cc: alexander.deucher@amd.com, harry.wentland@amd.com
Subject: Re: [PATCH] drm/amd/display: Fix register definitions for DCN32/321
Date: Tue, 6 Sep 2022 11:56:55 -0400 [thread overview]
Message-ID: <80e61ba2-e888-9ecd-d32b-5abff09a5d02@amd.com> (raw)
In-Reply-To: <20220901192736.1171423-1-aurabindo.pillai@amd.com>
On 2022-09-01 15:27, Aurabindo Pillai wrote:
> [Why & How]
> Fix the instatiation sequence for MPC registers and add a few other
> missing register definitions that were ommited erroneously when copying
> them over to enable runtime initialization of reigster offsets for
> DCN32/321
>
> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
> ---
> .../drm/amd/display/dc/dcn32/dcn32_resource.c | 27 +--
> .../drm/amd/display/dc/dcn32/dcn32_resource.h | 216 ++++++++++++------
> .../amd/display/dc/dcn321/dcn321_resource.c | 24 +-
> 3 files changed, 166 insertions(+), 101 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
> index ef0a6d468a10..9d3b8568351e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
> @@ -461,22 +461,17 @@ static const struct dcn20_dsc_mask dsc_mask = {
> };
>
> static struct dcn30_mpc_registers mpc_regs;
> -#define dcn_mpc_regs_init()\
> - ( \
> - MPC_REG_LIST_DCN3_0_RI(0),\
> - MPC_REG_LIST_DCN3_0_RI(1),\
> - MPC_REG_LIST_DCN3_0_RI(2),\
> - MPC_REG_LIST_DCN3_0_RI(3),\
> - MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
> - MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
> - MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
> - MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
> - MPC_MCM_REG_LIST_DCN32_RI(0),\
> - MPC_MCM_REG_LIST_DCN32_RI(1),\
> - MPC_MCM_REG_LIST_DCN32_RI(2),\
> - MPC_MCM_REG_LIST_DCN32_RI(3),\
> - MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)\
> - )
> +
> +#define dcn_mpc_regs_init() \
> + MPC_REG_LIST_DCN3_2_RI(0),\
> + MPC_REG_LIST_DCN3_2_RI(1),\
> + MPC_REG_LIST_DCN3_2_RI(2),\
> + MPC_REG_LIST_DCN3_2_RI(3),\
> + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
> + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
> + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
> + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
> + MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
>
> static const struct dcn30_mpc_shift mpc_shift = {
> MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
> index 60d8fad16eee..4c931905223d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
> @@ -222,7 +222,8 @@ void dcn32_determine_det_override(struct dc_state *context, display_e2e_pipe_par
> SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \
> SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
> SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
> - SRI_ARR(DP_SEC_CNTL2, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
> + SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
> + SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
> SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \
> SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
> SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \
> @@ -735,75 +736,6 @@ void dcn32_determine_det_override(struct dc_state *context, display_e2e_pipe_par
> #define MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst) \
> SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst)
>
> -#define MPC_MCM_REG_LIST_DCN32_RI(inst) \
> - ( \
> - SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst), \
> - SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst) \
> - )
> -
> #define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst) \
> ( \
> SRII(MUX, MPC_OUT, inst), VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst) \
> @@ -887,6 +819,149 @@ void dcn32_determine_det_override(struct dc_state *context, display_e2e_pipe_par
> SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst) \
> )
>
> +#define MPC_REG_LIST_DCN3_2_RI(inst) \
> + MPC_REG_LIST_DCN3_0_RI(inst),\
> + SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\
> + SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst), /*TODO: may need to add other 3DLUT regs*/\
> + SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_2_3, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_4_5, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_6_7, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_8_9, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_10_11, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_12_13, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_14_15, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_16_17, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_18_19, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_20_21, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_22_23, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_24_25, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_26_27, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_28_29, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_30_31, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMA_REGION_32_33, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_B, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_G, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_R, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_0_1, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_2_3, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_4_5, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_6_7, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_8_9, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_10_11, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_12_13, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_14_15, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_16_17, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_18_19, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_20_21, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_22_23, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_24_25, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_26_27, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_28_29, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_30_31, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_1DLUT_RAMB_REGION_32_33, MPCC_MCM, inst),\
> + SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst)
> +
> /* OPTC */
>
> #define OPTC_COMMON_REG_LIST_DCN3_2_RI(inst) \
> @@ -1121,6 +1196,7 @@ void dcn32_determine_det_override(struct dc_state *context, display_e2e_pipe_par
> SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D), SR(DCHUBBUB_DET0_CTRL), \
> SR(DCHUBBUB_DET1_CTRL), SR(DCHUBBUB_DET2_CTRL), SR(DCHUBBUB_DET3_CTRL), \
> SR(DCHUBBUB_COMPBUF_CTRL), SR(COMPBUF_RESERVED_SPACE), \
> + SR(DCHUBBUB_DEBUG_CTRL_0), \
> SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL), \
> SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A), \
> SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B), \
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
> index a93dc00ebfb5..184997a5b464 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
> @@ -466,21 +466,15 @@ static const struct dcn20_dsc_mask dsc_mask = {
>
> static struct dcn30_mpc_registers mpc_regs;
> #define dcn_mpc_regs_init()\
> - ( \
> - MPC_REG_LIST_DCN3_0_RI(0),\
> - MPC_REG_LIST_DCN3_0_RI(1),\
> - MPC_REG_LIST_DCN3_0_RI(2),\
> - MPC_REG_LIST_DCN3_0_RI(3),\
> - MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
> - MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
> - MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
> - MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
> - MPC_MCM_REG_LIST_DCN32_RI(0),\
> - MPC_MCM_REG_LIST_DCN32_RI(1),\
> - MPC_MCM_REG_LIST_DCN32_RI(2),\
> - MPC_MCM_REG_LIST_DCN32_RI(3),\
> - MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)\
> - )
> + MPC_REG_LIST_DCN3_2_RI(0),\
> + MPC_REG_LIST_DCN3_2_RI(1),\
> + MPC_REG_LIST_DCN3_2_RI(2),\
> + MPC_REG_LIST_DCN3_2_RI(3),\
> + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
> + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
> + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
> + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
> + MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
>
> static const struct dcn30_mpc_shift mpc_shift = {
> MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
LGTM,
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
I asked Daniel to run a couple of tests with this patch. Let's wait for
his result before we merge it.
Thanks
Siqueira
next prev parent reply other threads:[~2022-09-06 15:57 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 19:27 [PATCH] drm/amd/display: Fix register definitions for DCN32/321 Aurabindo Pillai
2022-09-06 15:56 ` Rodrigo Siqueira Jordao [this message]
2022-09-06 21:00 ` Pillai, Aurabindo
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