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Dadhania" In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|BN5PR12MB9511:EE_ X-MS-Office365-Filtering-Correlation-Id: 7786c054-ce98-4b9f-908e-08de8007fb4c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|1800799024|36860700016|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: 2SEptjRlVPvBRr0HfygOVNcTNUumRx/f8ptz+xqSUaAQ56+8d6p5ySYCY0r0I26BAAB9tofI8PvXQ04FCReHBC5ERk/aaK2PkC5joo0n9YpaoIZ4lYecZGpefEBnNbQTGKeWP2+KqwTKGfTSE7YyNQ/W/gldJ/DwqWuYW6RiPjjB/SH/5A3ugAX+zM+JSMEDCHnP2ROKmnF0abDakQKXv4WNZMv6hNYV2Rs32Z61rS7UA7TNx+sA3ksyvi9ePZKRSMU+8zs/SYVGSWBqh/qa0kmFuDCaT9IEchzC/AZntICsp0LpOijxKNsMwDljLAt6Jxh8U5ZGlWoEHmdYerKX7kkI4qRIBT1crXCqYws9H7qHPk+gW49tE0szcgsufZ15cJVL4GmTaQk8sSGM6FbpSCLqye6XXvCEbDL8po+/3lh7RYcSryZsqsAzXCMGqBEV54RbKwxpuMpOPmk+mMPggY0gxxsCCJLRRSIQKstp7wtl4ltVgAEnH4IU0KLCDdf3gTFz5C4SFX5YwZpeopf0ZJ2QT6l/8M5PRdvUaOGvHziHRH1r5CnmerghLQUVdtizxUKL3CJUQfvpkruiRZwEU5a3x06B7ReAjqr1N6HCbHaKlv1XBFVL7Tr4p8Wc6Vs183qf0gXN5fzElAMQEJpLnh2RVj8w2l9l7zNwbkCaDGL869Hh8ujTm7p4m/ng674xQQCV4GDpsI/yVRHEQ29hyU9e8UIv7hIIAWOplZtqqL2MeOfs9Z/GbMXRmWCfp4745R+K+zuQt8Mo9FFGWhGi6Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(1800799024)(36860700016)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4PyxUJLmFuhAvHIBs/+Oi5+Yyb47A3OJ6DR/t+cQwS/wXt2IFuq+riDWfCJToc7aG2lN9k8DRJnK0hp0B1n9fCNbAj/qfmZGI186ygBZO7FQgVLlvQN9trDQGbnGtkG37B/R9mJZf29GgyKUJUWz9DOO3nnArxGZQFnnpxB4nURaj3PxS60JBo1igqm4jIpksgPuN8B2Y9odY8B+VyvNwKODD/T5AkNxcoc4o0vuuACXho8hAX4qE+6xjuqfW1rdLI8orxrKyRekohVTnN15t5Tur8R2R8R2JrNRu6wLgNAOA4fbjGq21+lM9zC+6vTxd0DMmKyc8CD9DHaf0FyrV/u+/Ai5ScUKF4ANpFHxxwyHYnDAzWoeT3Vk0B/gocPsqygyUDUtHBpB6fY94fvIuKNOcenMfMs+7PLnDz3OyJlAIq2zo8xwcUY+Cb2CFw9k X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2026 07:21:30.1917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7786c054-ce98-4b9f-908e-08de8007fb4c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9511 On 3/11/2026 10:58 PM, Dave Hansen wrote: > On 3/11/26 08:42, Nikunj A. Dadhania wrote: >> -void cr4_init(void) >> +void cr4_init(bool boot_cpu) > > I think the "pass a bool to a function" pattern is really not great. The reason I introduced it was to avoid double-enabling PCIDE on the boot CPU. The boot CPU already enables PCIDE via setup_pcid(). > The problem isn't actually setting CR4 twice. The problem is having two > different code paths to set it. Doing the 'bool' doesn't eliminate the > code path, it just makes the whole thing more complicated to reason > about and further bifurcates the boot and secondary CPU bringup paths. > > We want to unify those, not bifurcate them. > > Why don't we just universally set X86_CR4_FSGSBASE in cr4_init()? Right, this approach becomes much simpler with the boot_cpu: diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 1c3261cae40c..6c0493eaf813 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -502,6 +502,17 @@ void cr4_init(void) if (boot_cpu_has(X86_FEATURE_PCID)) cr4 |= X86_CR4_PCIDE; + + /* + * CPUs that support FSGSBASE may use RDGSBASE/WRGSBASE in + * paranoid_entry(). Enable the feature before any exceptions + * occur. + */ + if (boot_cpu_has(X86_FEATURE_FSGSBASE)) { + cr4 |= X86_CR4_FSGSBASE; + elf_hwcap2 |= HWCAP2_FSGSBASE; + } + if (static_branch_likely(&cr_pinning)) cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; @@ -2047,12 +2058,6 @@ static void identify_cpu(struct cpuinfo_x86 *c) setup_umip(c); setup_lass(c); - /* Enable FSGSBASE instructions if available. */ - if (cpu_has(c, X86_FEATURE_FSGSBASE)) { - cr4_set_bits(X86_CR4_FSGSBASE); - elf_hwcap2 |= HWCAP2_FSGSBASE; - } - /* * The vendor-specific functions might have changed features. * Now we do "generic changes." diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 4dbff8ef9b1c..0a2b129bda03 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1685,6 +1685,13 @@ void __init trap_init(void) /* Init GHCB memory pages when running as an SEV-ES guest */ sev_es_init_vc_handling(); + /* + * Initialize CR4 early, before cpu_init(). This ensures features like + * FSGSBASE are enabled before exception handlers run, avoiding double + * initialization later. + */ + cr4_init(); + /* Initialize TSS before setting up traps so ISTs work */ cpu_init_exception_handling(true);