From: David Woodhouse <dwmw2@infradead.org>
To: Russ.Dill@asu.edu
Cc: mtd@infradead.org
Subject: Re: Supported flash memory
Date: Fri, 05 Jan 2001 16:29:09 +0000 [thread overview]
Message-ID: <8151.978712149@redhat.com> (raw)
In-Reply-To: <978711806.3a55f4fe37922@webmail1.asu.edu>
Russ.Dill@asu.edu said:
> What about flashes that say they have CUI (Command user interface)
> and SR (Status register)?
Not sure. I haven't encountered those.
> what are CFI commands? are they 8bit, 16bit?
Can be either.
> if you have 2 chips giving you a 32bit databus, does it write out the same
> command on the high lane and the low lane?
Yep.
Russ.Dill@asu.edu said:
> I've noticed LART connects address and data lines to flash in
> positions most convienent to route. Does this break any CFI
> functionality?
What do you mean? It's generally considered quite rude for hardware
designers to connect nets to _completely_ random places on the chips,
although sometimes it wouldn't really surprise me.
--
dwmw2
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next prev parent reply other threads:[~2001-01-05 16:29 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-01-04 19:28 Supported flash memory Russ.Dill
2001-01-05 12:05 ` David Woodhouse
2001-01-05 13:56 ` Kenneth Johansson
2001-01-05 14:09 ` David Woodhouse
[not found] ` <978711806.3a55f4fe37922@webmail1.asu.edu>
2001-01-05 16:29 ` David Woodhouse [this message]
2001-01-05 16:57 ` Kenneth Johansson
2001-01-05 17:03 ` David Woodhouse
2001-01-05 18:01 ` Nicolas Pitre
2001-01-05 21:07 ` David Woodhouse
2001-01-07 16:42 ` David Woodhouse
2001-01-05 17:53 ` Nicolas Pitre
-- strict thread matches above, loose matches on Subject: below --
2001-02-02 0:49 Supported Flash memory Jose Guilberto
2001-02-02 10:30 ` David Woodhouse
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