diff for duplicates of <8178382.Z7YODHSRMC@avalon> diff --git a/a/1.txt b/N1/1.txt index 46d70e6..e8f0eef 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,3 +1,286 @@ +From: Jakub Kicinski <jakub.kicinski@netronome.com> +Date: Thu, 7 Apr 2016 19:39:33 +0100 + +> I re-discussed MPLS/MTU internally, dropped it from the patch 1, +> re-tested everything, found out I forgot about debugfs pointers, +> fixed that as well. +> +> v5: +> - don't reserve space in RX buffers for MPLS label stack +> (patch 1); +> - fix debugfs pointers to ring structures (patch 5). +> v4: +> - cut down on unrelated patches; +> - don't "close" the device on error path. +> +> --- v4 cover letter +> +> Previous series included some not entirely related patches, +> this one is cut down. Main issue I'm trying to solve here +> is that .ndo_change_mtu() in nfpvf driver is doing full +> close/open to reallocate buffers - which if open fails +> can result in device being basically closed even though +> the interface is started. As suggested by you I try to move +> towards a paradigm where the resources are allocated first +> and the MTU change is only done once I'm certain (almost) +> nothing can fail. Almost because I need to communicate +> with FW and that can always time out. +> +> Patch 1 fixes small issue. Next 10 patches reorganize things +> so that I can easily allocate new rings and sets of buffers +> while the device is running. Patches 13 and 15 reshape the +> .ndo_change_mtu() and ethtool's ring-resize operation into +> desired form. + +Looks good, series applied, thanks! + +Add a BPF_F_CURRENT_CPU flag to optimize the use-case where user space has +per-CPU ring buffers and the eBPF program pushes the data into the current +CPU's ring buffer which saves us an extra helper function call in eBPF. +Also, make sure to properly reserve the remaining flags which are not used. + +Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> +Signed-off-by: Alexei Starovoitov <ast@kernel.org> +--- + include/uapi/linux/bpf.h | 4 ++++ + kernel/trace/bpf_trace.c | 7 ++++++- + 2 files changed, 10 insertions(+), 1 deletion(-) + +diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h +index 70eda5a..b7b0fb1 100644 +--- a/include/uapi/linux/bpf.h ++++ b/include/uapi/linux/bpf.h +@@ -347,6 +347,10 @@ enum bpf_func_id { + #define BPF_F_ZERO_CSUM_TX (1ULL << 1) + #define BPF_F_DONT_FRAGMENT (1ULL << 2) + ++/* BPF_FUNC_perf_event_output flags. */ ++#define BPF_F_INDEX_MASK 0xffffffffULL ++#define BPF_F_CURRENT_CPU BPF_F_INDEX_MASK ++ + /* user accessible mirror of in-kernel sk_buff. + * new fields can only be added to the end of this structure + */ +diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c +index 6855878..6bfe55c 100644 +--- a/kernel/trace/bpf_trace.c ++++ b/kernel/trace/bpf_trace.c +@@ -225,11 +225,12 @@ static const struct bpf_func_proto bpf_perf_event_read_proto = { + .arg2_type = ARG_ANYTHING, + }; + +-static u64 bpf_perf_event_output(u64 r1, u64 r2, u64 index, u64 r4, u64 size) ++static u64 bpf_perf_event_output(u64 r1, u64 r2, u64 flags, u64 r4, u64 size) + { + struct pt_regs *regs = (struct pt_regs *) (long) r1; + struct bpf_map *map = (struct bpf_map *) (long) r2; + struct bpf_array *array = container_of(map, struct bpf_array, map); ++ u64 index = flags & BPF_F_INDEX_MASK; + void *data = (void *) (long) r4; + struct perf_sample_data sample_data; + struct perf_event *event; +@@ -239,6 +240,10 @@ static u64 bpf_perf_event_output(u64 r1, u64 r2, u64 index, u64 r4, u64 size) + .data = data, + }; + ++ if (unlikely(flags & ~(BPF_F_INDEX_MASK))) ++ return -EINVAL; ++ if (index == BPF_F_CURRENT_CPU) ++ index = raw_smp_processor_id(); + if (unlikely(index >= array->map.max_entries)) + return -E2BIG; + +-- +1.9.3 + +From: Wolfram Sang <wsa+renesas@sang-engineering.com> + +Looking at the backlogs, I am not the only one who missed that the above +functions do not read u32 from one register, but create a virtual u32 +from reading to adjacent u16 registers (which depending on 'bus_shift' +can be up to 8 byte apart). Because this driver supports old hardware +for which we don't have documentation, I first wrongly assumed there was +a variant which had a few u32 registers. Let's give the functions more +descriptive names to make it more obvious what is happening. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc.h | 5 ++--- + drivers/mmc/host/tmio_mmc_pio.c | 22 +++++++++++----------- + 2 files changed, 13 insertions(+), 14 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h +index 439fdad2bad91d..e75e5ca220bc0a 100644 +--- a/drivers/mmc/host/tmio_mmc.h ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -232,7 +232,7 @@ static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr, + readsw(host->ctl + (addr << host->bus_shift), buf, count); + } + +-static inline u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr) ++static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, int addr) + { + return readw(host->ctl + (addr << host->bus_shift)) | + readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16; +@@ -254,11 +254,10 @@ static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr, + writesw(host->ctl + (addr << host->bus_shift), buf, count); + } + +-static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val) ++static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int addr, u32 val) + { + writew(val, host->ctl + (addr << host->bus_shift)); + writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); + } + +- + #endif +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 15e6f6d5a42337..dad2ebd3dc22b4 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -55,18 +55,18 @@ + void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i) + { + host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ); +- sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask); ++ sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask); + } + + void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i) + { + host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ); +- sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask); ++ sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask); + } + + static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i) + { +- sd_ctrl_write32(host, CTL_STATUS, ~i); ++ sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, ~i); + } + + static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data) +@@ -381,7 +381,7 @@ static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command + tmio_mmc_enable_mmc_irqs(host, irq_mask); + + /* Fire off the command */ +- sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg); ++ sd_ctrl_write32_as_16_and_16(host, CTL_ARG_REG, cmd->arg); + sd_ctrl_write16(host, CTL_SD_CMD, c); + + return 0; +@@ -536,7 +536,7 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host) + goto out; + + if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) { +- u32 status = sd_ctrl_read32(host, CTL_STATUS); ++ u32 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS); + bool done = false; + + /* +@@ -591,7 +591,7 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, + */ + + for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4) +- cmd->resp[i] = sd_ctrl_read32(host, addr); ++ cmd->resp[i] = sd_ctrl_read16_and_16_as_32(host, addr); + + if (cmd->flags & MMC_RSP_136) { + cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24); +@@ -708,14 +708,14 @@ irqreturn_t tmio_mmc_irq(int irq, void *devid) + struct tmio_mmc_host *host = devid; + unsigned int ireg, status; + +- status = sd_ctrl_read32(host, CTL_STATUS); ++ status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS); + ireg = status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask; + + pr_debug_status(status); + pr_debug_status(ireg); + + /* Clear the status except the interrupt status */ +- sd_ctrl_write32(host, CTL_STATUS, TMIO_MASK_IRQ); ++ sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, TMIO_MASK_IRQ); + + if (__tmio_mmc_card_detect_irq(host, ireg, status)) + return IRQ_HANDLED; +@@ -961,7 +961,7 @@ static int tmio_mmc_get_ro(struct mmc_host *mmc) + + pm_runtime_get_sync(mmc_dev(mmc)); + ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) || +- (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)); ++ (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)); + pm_runtime_mark_last_busy(mmc_dev(mmc)); + pm_runtime_put_autosuspend(mmc_dev(mmc)); + +@@ -983,7 +983,7 @@ static int tmio_mmc_card_busy(struct mmc_host *mmc) + { + struct tmio_mmc_host *host = mmc_priv(mmc); + +- return !(sd_ctrl_read32(host, CTL_STATUS2) & TMIO_STATUS2_DAT0); ++ return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS2) & TMIO_STATUS2_DAT0); + } + + static struct mmc_host_ops tmio_mmc_ops = { +@@ -1132,7 +1132,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host, + tmio_mmc_clk_stop(_host); + tmio_mmc_reset(_host); + +- _host->sdcard_irq_mask = sd_ctrl_read32(_host, CTL_IRQ_MASK); ++ _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK); + tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL); + + /* Unmask the IRQs we want to know about */ +-- +2.7.0 + +From: Jiri Pirko <jiri@resnulli.us> +Date: Fri, 8 Apr 2016 17:51:55 +0200 + +> Fri, Apr 08, 2016 at 05:45:20PM CEST, jiri@resnulli.us wrote: +>>From: Jiri Pirko <jiri@mellanox.com> +>> +>>Cosmetics, in preparation to sharedbuffer patchset. +> +> Dave, I just realized there is dependency on: +> "devlink: remove implicit type set in port register" which I sent couple +> of minutes after this patchset. I can either resend in bulk, or if you +> could apply in order, that would be great. + +The devlink series also lacked a header posting. Can you just sort this +all out properly and respin everything? + +Thanks. + +> Thanks and sorry, owe you another beer :) + +:-) + +On Thu, Apr 7, 2016 at 7:32 PM, Alexander Duyck <aduyck@mirantis.com> wrote: +> This patch adds support for a feature I am calling IP ID mangling. It is +> basically just another way of saying the IP IDs that are transmitted by the +> tunnel may not match up with what would normally be expected. Specifically +> what will happen is in the case of TSO the IP IDs on the headers will be a +> fixed value so a given TSO will repeat the same inner IP ID value gso_segs +> number of times. +> +> Signed-off-by: Alexander Duyck <aduyck@mirantis.com> + +If I'm understanding this correctly, enabling IP ID mangling will help +performance on ixgbe since it will allow it to do GSO partial instead +of plain GSO but it will hurt performance on i40e since it will drop +from TSO to plain GSO. + +Assuming that's right, it seems like it will make it hard to chose the +right setting without knowledge of which hardware is in use. I guess +what we really want is "I care about nicely incrementing IP IDs" vs. +"I don't care as long as the DF bit is set". That second case is +really what this flag is trying to say but it seems like it is +enforcing too much in the i40e case - I don't think anyone wants to go +out of their way to make IP IDs jump around if incrementing is faster. + On Friday 19 Feb 2016 11:59:40 Marc Zyngier wrote: > On 19/02/16 09:18, Linus Walleij wrote: > > Top-quoting so everyone on the new To:-line gets the context. @@ -83,3 +366,55 @@ can't call the synchronous version of the PM runtime functions. Regards, Laurent Pinchart + +Enables PWM1 (brightness control) and PWM2 (PMIC switching frequency +synchronization). + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> + +--- +arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 23 ++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +index 507d6a4..5525637 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +@@ -189,6 +189,15 @@ + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + ++ pwm1_pins: pwm1 { ++ renesas,groups = "pwm1_a"; ++ renesas,function = "pwm1"; ++ }; ++ pwm2_pins: pwm2 { ++ renesas,groups = "pwm2_a"; ++ renesas,function = "pwm2"; ++ }; ++ + scif1_pins: scif1 { + renesas,groups = "scif1_data_a", "scif1_ctrl"; + renesas,function = "scif1"; +@@ -299,6 +308,20 @@ + }; + }; + ++&pwm1 { ++ /* brightness control */ ++ pinctrl-0 = <&pwm1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&pwm2 { ++ /* PMIC DC/DC switching frequency synchronization */ ++ pinctrl-0 = <&pwm2_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ + &rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; diff --git a/a/content_digest b/N1/content_digest index 9625bbc..711566b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,66 @@ + "ref\01460130325-14931-1-git-send-email-jiri@resnulli.us\0" + "ref\020160407222211.11142.41024.stgit@ahduyck-xeon-server\0" "ref\01455811590-15836-1-git-send-email-geert+renesas@glider.be\0" "ref\0CACRpkdZ2zzP5u4uJDzsnks7ywrp3ddBt+YfxthJ+5mT-ECYLpg@mail.gmail.com\0" + "ref\01460054388-471-1-git-send-email-jakub.kicinski@netronome.com\0" + "ref\0cover.1461005139.git.daniel@iogearbox.net\0" + "ref\01461689625-3693-1-git-send-email-wsa@the-dreams.de\0" + "ref\020160408155155.GC1932@nanopsycho.orion\0" + "ref\020160407223237.11142.33072.stgit@ahduyck-xeon-server\0" "ref\056C703AC.4040803@arm.com\0" + "From\0David Miller <davem@davemloft.net>\0" + "From\0Daniel Borkmann <daniel@iogearbox.net>\0" + "From\0Wolfram Sang <wsa@the-dreams.de>\0" + "From\0David Miller <davem@davemloft.net>\0" + "From\0Jesse Gross <jesse@kernel.org>\0" "From\0Laurent Pinchart <laurent.pinchart@ideasonboard.com>\0" + "From\0Ulrich Hecht <ulrich.hecht+renesas@gmail.com>\0" + "Subject\0Re: [PATCH v5 net-next 00/15] MTU/buffer reconfig changes\0" + "Subject\0[PATCH net-next v2 1/2] bpf, trace: add BPF_F_CURRENT_CPU flag for bpf_perf_event_output\0" + "Subject\0[PATCH v2 1/5] mmc: tmio: give read32/write32 functions more descriptive names\0" + "Subject\0Re: [patch net-next 0/5] mlxsw: small driver update\0" + "Subject\0Re: [RFC PATCH 07/11] GENEVE: Add option to mangle IP IDs on inner headers when using TSO\0" "Subject\0Re: [PATCH/RFC v2] gpio: rcar: Add Runtime PM handling for interrupts\0" + "Subject\0[v3,4/6] arm64: dts: salvator-x: enable PWM\0" + "Date\0Fri, 08 Apr 2016 15:34:32 -0400 (EDT)\0" + "Date\0Mon, 18 Apr 2016 21:01:23 +0200\0" + "Date\0Tue, 26 Apr 2016 18:53:41 +0200\0" + "Date\0Fri, 08 Apr 2016 13:07:37 -0400 (EDT)\0" + "Date\0Thu, 7 Apr 2016 20:22:57 -0300\0" "Date\0Mon, 11 Apr 2016 19:26:09 +0300\0" + "Date\0Thu, 31 Mar 2016 13:39:14 +0200\0" + "To\0jakub.kicinski@netronome.com\0" + "To\0davem@davemloft.net\0" + "To\0linux-mmc@vger.kernel.org\0" + "To\0jiri@resnulli.us\0" + "To\0Alexander Duyck <aduyck@mirantis.com>\0" "To\0Marc Zyngier <marc.zyngier@arm.com>\0" + "To\0linux-renesas-soc@vger.kernel.org" + " geert@linux-m68k.org\0" + "Cc\0netdev@vger.kernel.org\0" + "Cc\0alexei.starovoitov@gmail.com" + tgraf@suug.ch + netdev@vger.kernel.org + linux-kernel@vger.kernel.org + Daniel Borkmann <daniel@iogearbox.net> + " Alexei Starovoitov <ast@kernel.org>\0" + "Cc\0Wolfram Sang <wsa@the-dreams.de>" + linux-renesas-soc@vger.kernel.org + Ulf Hansson <ulf.hansson@linaro.org> + " Simon Horman <horms+renesas@verge.net.au>\0" + "Cc\0netdev@vger.kernel.org" + idosch@mellanox.com + eladr@mellanox.com + yotamg@mellanox.com + ogerlitz@mellanox.com + roopa@cumulusnetworks.com + " gospo@cumulusnetworks.com\0" + "Cc\0herbert@gondor.apana.org.au" + Tom Herbert <tom@herbertland.com> + Alexander Duyck <alexander.duyck@gmail.com> + edumazet@google.com + Linux Kernel Network Developers <netdev@vger.kernel.org> + " David Miller <davem@davemloft.net>\0" "Cc\0Linus Walleij <linus.walleij@linaro.org>" Geert Uytterhoeven <geert+renesas@glider.be> Thomas Gleixner <tglx@linutronix.de> @@ -16,8 +72,295 @@ linux-gpio@vger.kernel.org <linux-gpio@vger.kernel.org> linux-pm@vger.kernel.org <linux-pm@vger.kernel.org> " linux-renesas-soc@vger.kernel.org\0" + "Cc\0linux-pwm@vger.kernel.org" + thierry.reding@gmail.com + magnus.damm@gmail.com + " Ulrich Hecht <ulrich.hecht+renesas@gmail.com>\0" "\00:1\0" "b\0" + "From: Jakub Kicinski <jakub.kicinski@netronome.com>\n" + "Date: Thu, 7 Apr 2016 19:39:33 +0100\n" + "\n" + "> I re-discussed MPLS/MTU internally, dropped it from the patch 1,\n" + "> re-tested everything, found out I forgot about debugfs pointers,\n" + "> fixed that as well.\n" + "> \n" + "> v5:\n" + "> - don't reserve space in RX buffers for MPLS label stack\n" + "> (patch 1);\n" + "> - fix debugfs pointers to ring structures (patch 5).\n" + "> v4:\n" + "> - cut down on unrelated patches;\n" + "> - don't \"close\" the device on error path.\n" + "> \n" + "> --- v4 cover letter\n" + "> \n" + "> Previous series included some not entirely related patches,\n" + "> this one is cut down. Main issue I'm trying to solve here\n" + "> is that .ndo_change_mtu() in nfpvf driver is doing full\n" + "> close/open to reallocate buffers - which if open fails\n" + "> can result in device being basically closed even though\n" + "> the interface is started. As suggested by you I try to move\n" + "> towards a paradigm where the resources are allocated first\n" + "> and the MTU change is only done once I'm certain (almost)\n" + "> nothing can fail. Almost because I need to communicate \n" + "> with FW and that can always time out.\n" + "> \n" + "> Patch 1 fixes small issue. Next 10 patches reorganize things\n" + "> so that I can easily allocate new rings and sets of buffers\n" + "> while the device is running. Patches 13 and 15 reshape the\n" + "> .ndo_change_mtu() and ethtool's ring-resize operation into\n" + "> desired form.\n" + "\n" + "Looks good, series applied, thanks!\n" + "\n" + "Add a BPF_F_CURRENT_CPU flag to optimize the use-case where user space has\n" + "per-CPU ring buffers and the eBPF program pushes the data into the current\n" + "CPU's ring buffer which saves us an extra helper function call in eBPF.\n" + "Also, make sure to properly reserve the remaining flags which are not used.\n" + "\n" + "Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>\n" + "Signed-off-by: Alexei Starovoitov <ast@kernel.org>\n" + "---\n" + " include/uapi/linux/bpf.h | 4 ++++\n" + " kernel/trace/bpf_trace.c | 7 ++++++-\n" + " 2 files changed, 10 insertions(+), 1 deletion(-)\n" + "\n" + "diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h\n" + "index 70eda5a..b7b0fb1 100644\n" + "--- a/include/uapi/linux/bpf.h\n" + "+++ b/include/uapi/linux/bpf.h\n" + "@@ -347,6 +347,10 @@ enum bpf_func_id {\n" + " #define BPF_F_ZERO_CSUM_TX\t\t(1ULL << 1)\n" + " #define BPF_F_DONT_FRAGMENT\t\t(1ULL << 2)\n" + " \n" + "+/* BPF_FUNC_perf_event_output flags. */\n" + "+#define BPF_F_INDEX_MASK\t\t0xffffffffULL\n" + "+#define BPF_F_CURRENT_CPU\t\tBPF_F_INDEX_MASK\n" + "+\n" + " /* user accessible mirror of in-kernel sk_buff.\n" + " * new fields can only be added to the end of this structure\n" + " */\n" + "diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c\n" + "index 6855878..6bfe55c 100644\n" + "--- a/kernel/trace/bpf_trace.c\n" + "+++ b/kernel/trace/bpf_trace.c\n" + "@@ -225,11 +225,12 @@ static const struct bpf_func_proto bpf_perf_event_read_proto = {\n" + " \t.arg2_type\t= ARG_ANYTHING,\n" + " };\n" + " \n" + "-static u64 bpf_perf_event_output(u64 r1, u64 r2, u64 index, u64 r4, u64 size)\n" + "+static u64 bpf_perf_event_output(u64 r1, u64 r2, u64 flags, u64 r4, u64 size)\n" + " {\n" + " \tstruct pt_regs *regs = (struct pt_regs *) (long) r1;\n" + " \tstruct bpf_map *map = (struct bpf_map *) (long) r2;\n" + " \tstruct bpf_array *array = container_of(map, struct bpf_array, map);\n" + "+\tu64 index = flags & BPF_F_INDEX_MASK;\n" + " \tvoid *data = (void *) (long) r4;\n" + " \tstruct perf_sample_data sample_data;\n" + " \tstruct perf_event *event;\n" + "@@ -239,6 +240,10 @@ static u64 bpf_perf_event_output(u64 r1, u64 r2, u64 index, u64 r4, u64 size)\n" + " \t\t.data = data,\n" + " \t};\n" + " \n" + "+\tif (unlikely(flags & ~(BPF_F_INDEX_MASK)))\n" + "+\t\treturn -EINVAL;\n" + "+\tif (index == BPF_F_CURRENT_CPU)\n" + "+\t\tindex = raw_smp_processor_id();\n" + " \tif (unlikely(index >= array->map.max_entries))\n" + " \t\treturn -E2BIG;\n" + " \n" + "-- \n" + "1.9.3\n" + "\n" + "From: Wolfram Sang <wsa+renesas@sang-engineering.com>\n" + "\n" + "Looking at the backlogs, I am not the only one who missed that the above\n" + "functions do not read u32 from one register, but create a virtual u32\n" + "from reading to adjacent u16 registers (which depending on 'bus_shift'\n" + "can be up to 8 byte apart). Because this driver supports old hardware\n" + "for which we don't have documentation, I first wrongly assumed there was\n" + "a variant which had a few u32 registers. Let's give the functions more\n" + "descriptive names to make it more obvious what is happening.\n" + "\n" + "Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>\n" + "Reviewed-by: Simon Horman <horms+renesas@verge.net.au>\n" + "---\n" + " drivers/mmc/host/tmio_mmc.h | 5 ++---\n" + " drivers/mmc/host/tmio_mmc_pio.c | 22 +++++++++++-----------\n" + " 2 files changed, 13 insertions(+), 14 deletions(-)\n" + "\n" + "diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h\n" + "index 439fdad2bad91d..e75e5ca220bc0a 100644\n" + "--- a/drivers/mmc/host/tmio_mmc.h\n" + "+++ b/drivers/mmc/host/tmio_mmc.h\n" + "@@ -232,7 +232,7 @@ static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,\n" + " \treadsw(host->ctl + (addr << host->bus_shift), buf, count);\n" + " }\n" + " \n" + "-static inline u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)\n" + "+static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, int addr)\n" + " {\n" + " \treturn readw(host->ctl + (addr << host->bus_shift)) |\n" + " \t readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;\n" + "@@ -254,11 +254,10 @@ static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,\n" + " \twritesw(host->ctl + (addr << host->bus_shift), buf, count);\n" + " }\n" + " \n" + "-static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)\n" + "+static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int addr, u32 val)\n" + " {\n" + " \twritew(val, host->ctl + (addr << host->bus_shift));\n" + " \twritew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));\n" + " }\n" + " \n" + "-\n" + " #endif\n" + "diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c\n" + "index 15e6f6d5a42337..dad2ebd3dc22b4 100644\n" + "--- a/drivers/mmc/host/tmio_mmc_pio.c\n" + "+++ b/drivers/mmc/host/tmio_mmc_pio.c\n" + "@@ -55,18 +55,18 @@\n" + " void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)\n" + " {\n" + " \thost->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);\n" + "-\tsd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);\n" + "+\tsd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);\n" + " }\n" + " \n" + " void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)\n" + " {\n" + " \thost->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);\n" + "-\tsd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);\n" + "+\tsd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);\n" + " }\n" + " \n" + " static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)\n" + " {\n" + "-\tsd_ctrl_write32(host, CTL_STATUS, ~i);\n" + "+\tsd_ctrl_write32_as_16_and_16(host, CTL_STATUS, ~i);\n" + " }\n" + " \n" + " static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)\n" + "@@ -381,7 +381,7 @@ static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command\n" + " \ttmio_mmc_enable_mmc_irqs(host, irq_mask);\n" + " \n" + " \t/* Fire off the command */\n" + "-\tsd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);\n" + "+\tsd_ctrl_write32_as_16_and_16(host, CTL_ARG_REG, cmd->arg);\n" + " \tsd_ctrl_write16(host, CTL_SD_CMD, c);\n" + " \n" + " \treturn 0;\n" + "@@ -536,7 +536,7 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host)\n" + " \t\tgoto out;\n" + " \n" + " \tif (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {\n" + "-\t\tu32 status = sd_ctrl_read32(host, CTL_STATUS);\n" + "+\t\tu32 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);\n" + " \t\tbool done = false;\n" + " \n" + " \t\t/*\n" + "@@ -591,7 +591,7 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,\n" + " \t */\n" + " \n" + " \tfor (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)\n" + "-\t\tcmd->resp[i] = sd_ctrl_read32(host, addr);\n" + "+\t\tcmd->resp[i] = sd_ctrl_read16_and_16_as_32(host, addr);\n" + " \n" + " \tif (cmd->flags & MMC_RSP_136) {\n" + " \t\tcmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);\n" + "@@ -708,14 +708,14 @@ irqreturn_t tmio_mmc_irq(int irq, void *devid)\n" + " \tstruct tmio_mmc_host *host = devid;\n" + " \tunsigned int ireg, status;\n" + " \n" + "-\tstatus = sd_ctrl_read32(host, CTL_STATUS);\n" + "+\tstatus = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);\n" + " \tireg = status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;\n" + " \n" + " \tpr_debug_status(status);\n" + " \tpr_debug_status(ireg);\n" + " \n" + " \t/* Clear the status except the interrupt status */\n" + "-\tsd_ctrl_write32(host, CTL_STATUS, TMIO_MASK_IRQ);\n" + "+\tsd_ctrl_write32_as_16_and_16(host, CTL_STATUS, TMIO_MASK_IRQ);\n" + " \n" + " \tif (__tmio_mmc_card_detect_irq(host, ireg, status))\n" + " \t\treturn IRQ_HANDLED;\n" + "@@ -961,7 +961,7 @@ static int tmio_mmc_get_ro(struct mmc_host *mmc)\n" + " \n" + " \tpm_runtime_get_sync(mmc_dev(mmc));\n" + " \tret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||\n" + "-\t\t(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));\n" + "+\t\t(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));\n" + " \tpm_runtime_mark_last_busy(mmc_dev(mmc));\n" + " \tpm_runtime_put_autosuspend(mmc_dev(mmc));\n" + " \n" + "@@ -983,7 +983,7 @@ static int tmio_mmc_card_busy(struct mmc_host *mmc)\n" + " {\n" + " \tstruct tmio_mmc_host *host = mmc_priv(mmc);\n" + " \n" + "-\treturn !(sd_ctrl_read32(host, CTL_STATUS2) & TMIO_STATUS2_DAT0);\n" + "+\treturn !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS2) & TMIO_STATUS2_DAT0);\n" + " }\n" + " \n" + " static struct mmc_host_ops tmio_mmc_ops = {\n" + "@@ -1132,7 +1132,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,\n" + " \ttmio_mmc_clk_stop(_host);\n" + " \ttmio_mmc_reset(_host);\n" + " \n" + "-\t_host->sdcard_irq_mask = sd_ctrl_read32(_host, CTL_IRQ_MASK);\n" + "+\t_host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);\n" + " \ttmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);\n" + " \n" + " \t/* Unmask the IRQs we want to know about */\n" + "-- \n" + "2.7.0\n" + "\n" + "From: Jiri Pirko <jiri@resnulli.us>\n" + "Date: Fri, 8 Apr 2016 17:51:55 +0200\n" + "\n" + "> Fri, Apr 08, 2016 at 05:45:20PM CEST, jiri@resnulli.us wrote:\n" + ">>From: Jiri Pirko <jiri@mellanox.com>\n" + ">>\n" + ">>Cosmetics, in preparation to sharedbuffer patchset.\n" + "> \n" + "> Dave, I just realized there is dependency on:\n" + "> \"devlink: remove implicit type set in port register\" which I sent couple\n" + "> of minutes after this patchset. I can either resend in bulk, or if you\n" + "> could apply in order, that would be great.\n" + "\n" + "The devlink series also lacked a header posting. Can you just sort this\n" + "all out properly and respin everything?\n" + "\n" + "Thanks.\n" + "\n" + "> Thanks and sorry, owe you another beer :)\n" + "\n" + ":-)\n" + "\n" + "On Thu, Apr 7, 2016 at 7:32 PM, Alexander Duyck <aduyck@mirantis.com> wrote:\n" + "> This patch adds support for a feature I am calling IP ID mangling. It is\n" + "> basically just another way of saying the IP IDs that are transmitted by the\n" + "> tunnel may not match up with what would normally be expected. Specifically\n" + "> what will happen is in the case of TSO the IP IDs on the headers will be a\n" + "> fixed value so a given TSO will repeat the same inner IP ID value gso_segs\n" + "> number of times.\n" + ">\n" + "> Signed-off-by: Alexander Duyck <aduyck@mirantis.com>\n" + "\n" + "If I'm understanding this correctly, enabling IP ID mangling will help\n" + "performance on ixgbe since it will allow it to do GSO partial instead\n" + "of plain GSO but it will hurt performance on i40e since it will drop\n" + "from TSO to plain GSO.\n" + "\n" + "Assuming that's right, it seems like it will make it hard to chose the\n" + "right setting without knowledge of which hardware is in use. I guess\n" + "what we really want is \"I care about nicely incrementing IP IDs\" vs.\n" + "\"I don't care as long as the DF bit is set\". That second case is\n" + "really what this flag is trying to say but it seems like it is\n" + "enforcing too much in the i40e case - I don't think anyone wants to go\n" + "out of their way to make IP IDs jump around if incrementing is faster.\n" + "\n" "On Friday 19 Feb 2016 11:59:40 Marc Zyngier wrote:\n" "> On 19/02/16 09:18, Linus Walleij wrote:\n" "> > Top-quoting so everyone on the new To:-line gets the context.\n" @@ -102,6 +445,58 @@ "-- \n" "Regards,\n" "\n" - Laurent Pinchart + "Laurent Pinchart\n" + "\n" + "Enables PWM1 (brightness control) and PWM2 (PMIC switching frequency\n" + "synchronization).\n" + "\n" + "Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>\n" + "Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>\n" + "\n" + "---\n" + "arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 23 ++++++++++++++++++++++\n" + " 1 file changed, 23 insertions(+)\n" + "\n" + "diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts\n" + "index 507d6a4..5525637 100644\n" + "--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts\n" + "+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts\n" + "@@ -189,6 +189,15 @@\n" + " \tpinctrl-0 = <&scif_clk_pins>;\n" + " \tpinctrl-names = \"default\";\n" + " \n" + "+\tpwm1_pins: pwm1 {\n" + "+\t\trenesas,groups = \"pwm1_a\";\n" + "+\t\trenesas,function = \"pwm1\";\n" + "+\t};\n" + "+\tpwm2_pins: pwm2 {\n" + "+\t\trenesas,groups = \"pwm2_a\";\n" + "+\t\trenesas,function = \"pwm2\";\n" + "+\t};\n" + "+\n" + " \tscif1_pins: scif1 {\n" + " \t\trenesas,groups = \"scif1_data_a\", \"scif1_ctrl\";\n" + " \t\trenesas,function = \"scif1\";\n" + "@@ -299,6 +308,20 @@\n" + " \t};\n" + " };\n" + " \n" + "+&pwm1 {\n" + "+\t/* brightness control */\n" + "+\tpinctrl-0 = <&pwm1_pins>;\n" + "+\tpinctrl-names = \"default\";\n" + "+\tstatus = \"okay\";\n" + "+};\n" + "+\n" + "+&pwm2 {\n" + "+\t/* PMIC DC/DC switching frequency synchronization */\n" + "+\tpinctrl-0 = <&pwm2_pins>;\n" + "+\tpinctrl-names = \"default\";\n" + "+\tstatus = \"okay\";\n" + "+};\n" + "+\n" + " &rcar_sound {\n" + " \tpinctrl-0 = <&sound_pins &sound_clk_pins>;\n" + " \tpinctrl-names = \"default\";" -c4bad5a3e442690771dd6c704036139ad1de8b0966ad0d71ccade869eff1199c +15669cb0c737d67aa1dcd369d17ca8a291413f070f19cc7398029bb20b5b0e5b
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