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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cee5d476esm444060935e9.1.2026.09.07.08.59.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Sep 2026 08:59:29 -0700 (PDT) Message-ID: <81aebdfa-b550-4ef9-8c7e-1009ff1d9bb9@redhat.com> Date: Mon, 7 Sep 2026 17:59:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC v5 23/28] hw/pci: Add sec-sid property to PCIDevice Content-Language: en-US To: Tao Tang , "Michael S . Tsirkin" , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Mostafa Saleh , Chao Liu , Jim MacArthur References: <20260813161515.2788900-1-tangtao1634@phytium.com.cn> <20260813162145.2800835-1-tangtao1634@phytium.com.cn> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/3/26 6:07 PM, Tao Tang wrote: > Hi Eric, > > On 2026/8/31 14:03, Eric Auger wrote: >> Hi Tao, >> >> On 8/13/26 6:21 PM, Tao Tang wrote: >>> Arm SMMUv3 uses a SEC_SID (StreamID Security state) to determine the >>> security state of the programming interface that controls a >>> transaction. >>> The architecture explicitly states that the association between a >>> device >>> and its SEC_SID is a system-defined property, not something derived >>> from >>> the physical address space. >>> >>> We need a way to represent this system-defined SEC_SID for PCI devices >>> if we want to implement SMMU's Secure state. So that SMMUv3 can select >>> the correct register bank and configuration when handling their >>> streams. >>> >>> This patch adds a new char *sec_sid field to PCIDevice, together with >>> a "sec-sid" QOM property. The property is intended to carry the >>> platform-defined SEC_SID for the device; for now only Non-secure and >>> Secure security states are supported. >> You shall add PCI maintainers in cc. >> >> Is it only SMMU intended? I mean if you set this property, the PCI >> device shall send DMA requests with secure attributes too? > > > Yes, the current consumer is Arm SMMUv3 only. The property represents > the system-defined SEC_SID presented to the SMMU, selecting its > programming interface and Stream table. It does not make the PCI > function issue DMA with Secure MemTxAttrs; that per-transaction > attribute is passed separately through attrs_to_index(). Some code > pieces:  yes you're right. Those are different. But how do you tell a device to send DMA transactions with attrs.secure (-> iommu_idx). That's what I am confused about. Do we plan to have a prop for that or will it be hardcoded such as in hw/misc/tz-mpc.c? > > ``` > static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, >                                       IOMMUAccessFlags flag, int > iommu_idx) > { > ..... >     SMMUv3State *s = sdev->smmu; >     SMMUSecSID sec_sid = sdev->sec_sid; >     SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid); > ..... >     entry.target_as = smmuv3_bypass_target_as(s, sec_sid, iommu_idx); > ...... >     if (!smmu_enabled(s, sec_sid)) { >         if (FIELD_EX32(bank->gbpa, GBPA, ABORT)) { >             status = SMMU_TRANS_ABORT; >         } else { >             status = SMMU_TRANS_DISABLE; >         } >         goto epilogue; >     } > ..... > } > ``` > > We use the device-inherent `PCIDevice->sec_sid` to select the SMMU > Programming Interface. The actual per-transaction attribute, on the > other hand, is passed to `smmuv3_translate()` through the `int > iommu_idx` parameter for each transaction. > > And Michael is already included in To: for both the cover letter and > this patch. I agree that this needs PCI maintainer review.  OK fine, sorry fo the noise.  Eric > > @Michael, Could you please help review this patch? > > Thanks, > Tao > > >> >> Eric >>> Signed-off-by: Tao Tang >>> Reviewed-by: Pierrick Bouvier >>> --- >>>   hw/pci/pci.c                | 7 +++++++ >>>   include/hw/pci/pci_device.h | 3 +++ >>>   2 files changed, 10 insertions(+) >>> >>> >