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This results in the driver configuring the wrong RF path, which leads to very poor reception. Users complain that 5 GHz networks are not visible. Hardcode the number of antennas for this RFE type to one, and the correct RF path for the Bluetooth coexistence code. This is what the vendor driver does. Closes: https://lore.kernel.org/linux-wireless/10543730.tdPhlSkOF2@topolinux/ Closes: https://github.com/morrownr/rtw89/issues/128 Signed-off-by: Bitterblue Smith --- drivers/net/wireless/realtek/rtw89/core.h | 1 + drivers/net/wireless/realtek/rtw89/mac.c | 5 +++++ drivers/net/wireless/realtek/rtw89/rtw8852b.c | 22 ++++++++++++++++++- 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h index 7e74b5c9ed49..71f00b07c77c 100644 --- a/drivers/net/wireless/realtek/rtw89/core.h +++ b/drivers/net/wireless/realtek/rtw89/core.h @@ -6529,6 +6529,7 @@ enum rtw89_quirks { RTW89_QUIRK_THERMAL_PROT_VCORE, RTW89_QUIRK_HW_INFO_SYSFS, RTW89_QUIRK_DISABLE_2GHZ, + RTW89_QUIRK_1ANT, NUM_OF_RTW89_QUIRKS, }; diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c index ad849e4b4a50..098b2372e65b 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.c +++ b/drivers/net/wireless/realtek/rtw89/mac.c @@ -3244,6 +3244,11 @@ static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev) tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); + if (test_bit(RTW89_QUIRK_1ANT, rtwdev->quirks)) { + tx_ant = 1; + rx_ant = 1; + } + hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b.c b/drivers/net/wireless/realtek/rtw89/rtw8852b.c index c3c53a6b8119..9d834ea36c1a 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852b.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852b.c @@ -353,6 +353,19 @@ static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = { static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; +static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, + enum rtw89_efuse_block block) +{ + int ret; + + ret = rtw8852bx_read_efuse(rtwdev, log_map, block); + + if (rtwdev->efuse.rfe_type == 41) + set_bit(RTW89_QUIRK_1ANT, rtwdev->quirks); + + return ret; +} + static void rtw8852b_pwr_sps_ana(struct rtw89_dev *rtwdev) { rtw89_write16(rtwdev, R_AX_SPS_ANA_ON_CTRL2, RTL8852B_DEFAULT_SPS_ANA); @@ -768,6 +781,13 @@ static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev) } else { md->ant.type = BTC_ANT_SHARED; md->bt0_pos = BTC_BT_BTG; + + if (test_bit(RTW89_QUIRK_1ANT, rtwdev->quirks)) { + md->ant.num = 1; + md->ant.single_pos = RF_PATH_B; + md->ant.btg_pos = RF_PATH_B; + md->ant.stream_cnt = 1; + } } rtwdev->btc.btg_pos = md->ant.btg_pos; rtwdev->btc.ant_type = md->ant.type; @@ -851,7 +871,7 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = { .write_rf = rtw89_phy_write_rf_v1, .set_channel = rtw8852b_set_channel, .set_channel_help = rtw8852b_set_channel_help, - .read_efuse = rtw8852bx_read_efuse, + .read_efuse = rtw8852b_read_efuse, .read_phycap = rtw8852bx_read_phycap, .fem_setup = NULL, .data_setup = NULL, -- 2.55.0