Re: [PATCH] drm/xe: Update register definitions in LRC layout header

["Summers, Stuart" <stuart.summers@intel.com>]

On Fri, 2025-07-11 at 06:09 +0000, Xin Wang wrote:
> Update the register definitions in xe_lrc_layout.h to align with the
> official hardware specification (Bspec) terminology. Specifically:
> 
> - rename PVC_CTX_ACC_CTR_THOLD to CTX_ACC_CTR_THOLD
> - rename PVC_CTX_ASID to CTX_ASID
> 
> Signed-off-by: Xin Wang <x.wang@intel.com>

Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_lrc_layout.h | 2 ++
>  drivers/gpu/drm/xe/xe_lrc.c             | 5 +----
>  2 files changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> index 994af591a2e8..e4cb1a487a37 100644
> --- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> +++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> @@ -15,6 +15,8 @@
>  #define CTX_TIMESTAMP                  (0x22 + 1)
>  #define CTX_TIMESTAMP_UDW              (0x24 + 1)
>  #define CTX_INDIRECT_RING_STATE                (0x26 + 1)
> +#define CTX_ACC_CTR_THOLD              (0x2a + 1)
> +#define CTX_ASID                       (0x2e + 1)
>  #define CTX_PDP0_UDW                   (0x30 + 1)
>  #define CTX_PDP0_LDW                   (0x32 + 1)
>  
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c
> b/drivers/gpu/drm/xe/xe_lrc.c
> index d2ad8fe737eb..452bcfa6cc6c 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -1031,9 +1031,6 @@ static int setup_wa_bb(struct xe_lrc *lrc,
> struct xe_hw_engine *hwe)
>         return -ENOSPC;
>  }
>  
> -#define PVC_CTX_ASID           (0x2e + 1)
> -#define PVC_CTX_ACC_CTR_THOLD  (0x2a + 1)
> -
>  static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
>                        struct xe_vm *vm, u32 ring_size, u16 msix_vec,
>                        u32 init_flags)
> @@ -1149,7 +1146,7 @@ static int xe_lrc_init(struct xe_lrc *lrc,
> struct xe_hw_engine *hwe,
>                 xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP_UDW, 0);
>  
>         if (xe->info.has_asid && vm)
> -               xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID, vm-
> >usm.asid);
> +               xe_lrc_write_ctx_reg(lrc, CTX_ASID, vm->usm.asid);
>  
>         lrc->desc = LRC_VALID;
>         lrc->desc |= FIELD_PREP(LRC_ADDRESSING_MODE,
> LRC_LEGACY_64B_CONTEXT);