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From: Tomi Sarvela <tomi.p.sarvela@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915: Rest of my DSI and DPLL stuff
Date: Thu, 14 Apr 2016 10:24:23 +0300	[thread overview]
Message-ID: <8397044.BClUR51EGa@fractal> (raw)
In-Reply-To: <20160413162925.GC4329@intel.com>


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On Wednesday 13 April 2016 19:29:25 Ville Syrjälä wrote:
[ILK-hp8440p problems]
> ...
> 
> [  265.316531] drm/i915: Resetting chip after gpu hang
> [  265.316585] [drm:i915_reset [i915]] *ERROR* Failed to reset chip: -110
> 
> Looks like the GPU died for some reason.
> 
> > Test kms_force_connector_basic:
> >         Subgroup prune-stale-modes:
> >                 pass       -> SKIP       (ivb-t430s)
> 
> No clue what happened here. The change isn't visible in the results
> visualization page, nor can I see this subtest even being run in
> the dmesg for Patchwork_1881. The dmesg ends at gtt-blt, but based on
> the json there were a ton of tests run after that. In fact the json
> and dmesg seem totally out of sync.
> 
> Tomi, any idea what's going on here?

The link from Patchwork page is hosed, but the full dmesgs are at
http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ilk-hp8440p/[1] 
http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ivb-t430s/[2] 

The dmesg is synced, but if the reset happens with delay, then it might be in wrong 
place. I'm suggesting to search for  test name and looking upwards from there.

> > Results at /archive/results/CI_IGT_test/Patchwork_1881/

Tomi

--------
[1] http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ilk-hp8440p/
[2] http://benchsrv.fi.intel.com/archive/results/CI_IGT_test/Patchwork_1881/ivb-t430s/

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  reply	other threads:[~2016-04-14  7:24 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-12 19:14 [PATCH 0/5] drm/i915: Rest of my DSI and DPLL stuff ville.syrjala
2016-04-12 19:14 ` [PATCH 1/5] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV ville.syrjala
2016-04-15 13:09   ` Jani Nikula
2016-04-15 13:27     ` Ville Syrjälä
2016-04-12 19:14 ` [PATCH 2/5] drm/i915: Compute DSI PLL parameters during .compute_config() ville.syrjala
2016-04-12 19:14 ` [PATCH 3/5] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll() ville.syrjala
2016-04-12 19:14 ` [PATCH 4/5] drm/i915: Hook up pfit for DSI ville.syrjala
2016-04-12 19:14 ` [PATCH 5/5] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms ville.syrjala
2016-04-13 16:02 ` ✗ Fi.CI.BAT: failure for drm/i915: Rest of my DSI and DPLL stuff Patchwork
2016-04-13 16:29   ` Ville Syrjälä
2016-04-14  7:24     ` Tomi Sarvela [this message]
2016-04-14  8:46       ` Ville Syrjälä
2016-04-14  8:54         ` Tomi Sarvela
2016-04-14  9:03           ` Ville Syrjälä
2016-04-15 12:52 ` [PATCH 0/5] " Jani Nikula

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