From: "Chee, Tien Fong" <tien.fong.chee@altera.com>
To: Tom Rini <trini@konsulko.com>
Cc: u-boot@lists.u-boot-project.org,
Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,
Dinesh Maniyam <dinesh.maniyam@altera.com>,
Chen Huei Lok <chen.huei.lok@altera.com>,
Brian Sune <briansune@gmail.com>,
Tze Yee Ng <tzeyee.ng@altera.com>, Peng Fan <peng.fan@nxp.com>,
Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>,
Marek Vasut <marek.vasut+renesas@mailbox.org>,
Boon Khai Ng <boon.khai.ng@altera.com>
Subject: Re: [GIT PULL] SoCFPGA updates for next (2026-08-17)
Date: Wed, 19 Aug 2026 09:16:43 +0800 [thread overview]
Message-ID: <83d2b4a9-ae55-46cb-9dbd-9d603fa1ec94@altera.com> (raw)
In-Reply-To: <20260818201715.GC523975@bill-the-cat>
Hi Tom,
On Tue, 18 Aug 2026 20:17:15 +0000, Tom Rini <trini@konsulko.com> wrote:
> I know CI doesn't fail on this, so I only saw it in my build logs:
> arm: w+ socfpga_de10_nano
> +(socfpga_de10_nano)
> +(socfpga_de10_nano) WARNING: unmet direct dependencies detected for DESIGNWARE_WATCHDOG
> +(socfpga_de10_nano) Depends on [n]: WDT [=n]
> +(socfpga_de10_nano) Selected by [y]:
> +(socfpga_de10_nano) - ARCH_SOCFPGA_CYCLONE5 [=y] && ARM [=y] && ARCH_SOCFPGA [=y] && !TARGET_SOCFPGA_TERASIC_SOCKIT [=n] && !TARGET_SOCFPGA_EBV_SOCRATES [=n] && !TARGET_SOCFPGA_SOFTING_VINING_FPGA [=n]
>
> That needs to be fixed.
Changelog since tags/u-boot-socfpga-next-20260817:
- arm: socfpga: cyclone5: select WDT with DESIGNWARE_WATCHDOG
ARCH_SOCFPGA_CYCLONE5 now selects WDT with the same board filter as
DESIGNWARE_WATCHDOG. socfpga_de10_nano no longer warns about the
unmet DESIGNWARE_WATCHDOG dependency.
This pull request updates SoCFPGA platforms with Stratix 10 and N5X
driver-model conversions, DDR robustness fixes, Agilex5 storage and DT
updates, and Gen5/Arria10 maintenance.
Stratix 10
Switch to the upstream Linux DT, combine boot-flash defconfigs, and move
firmware register settings into the device tree. Enable the system
manager driver, refactor the S10 clock driver, exclude S10 from legacy
MMC clkmgr address lookup, and improve SPL data save/restore and
watchdog support.
N5X
Enable the system manager driver and switch firewall setup to driver
model. Adopt the upstream Linux DT, update GMAC nodes, consolidate
ATF/VAB defconfigs, and use common SoC64 environment settings. Enable
CMD_MTD and ISSI QSPI, split the reset manager into common and
platform-family parts, and drop the kernel node from binman for the
non-VAB flow.
DDR and memory
Add ECC DRAM scrubbing and DRAM size checking for Gen5/Arria10,
secure-region support for the ATF flow, a delay before MBRDADDR writes,
and a data-cache flush fix. Use dev_read_addr_index_ptr() in the DDR
driver.
Agilex / Agilex5
Add an Agilex eMMC device tree, enable 8-bit eMMC, restrict watchdog0
autostart, set DTB filename and kernel-node removal for non-secure boot,
disable gmac2 on Agilex7M, and update Agilex PLL sync-to-async
configuration.
Gen5 / Arria10 and cleanup
Improve QTS handoff prepare isolation, fix the PL330 TARGET-to-ARCH
naming, enable DesignWare watchdog and random MAC on Arria10, select WDT
with DESIGNWARE_WATCHDOG on Cyclone V, and apply related Kconfig, FPGA,
clock and MAINTAINERS cleanups.
Please pull the updated tag.
The following changes since commit 527115ef6783cec49e5610c523c124b399011361:
pylibfdt: Replace removed SWIG Python 2 compatibility macros
(2026-08-13 10:12:41 -0600)
are available in the Git repository at:
https://git.u-boot-project.org/u-boot/custodians/u-boot-socfpga.git
tags/u-boot-socfpga-next-20260819
for you to fetch changes up to e80a7abab162936039d69864c697e4276d27470d:
arm: socfpga: cyclone5: select WDT with DESIGNWARE_WATCHDOG
(2026-08-19 08:38:02 +0800)
----------------------------------------------------------------
SoCFPGA updates for next (2026-08-19)
----------------------------------------------------------------
Alif Zakuan Yuslaimi (23):
arch: arm: dts: stratix10: Switch to using upstream Linux DT config
configs: stratix10: Combine defconfig for all boot flashes
arm: socfpga: Move firmware register settings from source code to
device tree
arm: socfpga: Update Stratix10 SPL data save and restore
implementation
arm: socfpga: s10: Enable system manager driver for Stratix10
ddr: altera: soc64: Add secure region support for ATF flow
clk: s10: Refactor S10 clock driver
mmc: socfpga_dw_mmc: Exclude S10 from legacy clkmgr address retrieval
spl: s10: Enhance watchdog support in SPL for Stratix 10
arm: socfpga: Consolidate dram_bank_mmu_setup()
ddr: altera: gen5: Add DRAM size checking
ddr: socfpga: Implement ECC DRAM scrubbing support for both
Gen5/Arria10
ddr: altera: arria10: Fix incorrect address for mpu1
arch: arm: dts: agilex5: Enable autostart on watchdog0 only
ddr: altera: Add delay before writing to MBRDADDR register
clk: altera: agilex: Update sync to async mode config in clk pll
arm: dts: agilex5: Set DTB filename and kernel node removal for
non-secure boot
configs: arria10: Enable random MAC address
arm: dts: socfpga: agilex: Add eMMC device tree source file
arch: arm: dts: agilex: Disable gmac2 node for Agilex7M
drivers: clk: n5x: Add support for enable/disable API
arm: dts: soc64: Remove kernel node from binman for non-VAB flow
arm: socfpga: n5x: Enable system manager driver for N5X
Boon Khai Ng (1):
configs: Enable CONFIG_WDT configurations for cyclone5
Brian Sune (2):
Fix old TARGET naming to ARCH for PL330
arm: socfpga: Improve handoff prepare on SoCFPGA
Chen Huei Lok (8):
configs: socfpga: n5x: consolidate ATF defconfig and simplify VAB
arm: dts: socfpga: n5x: update GMAC nodes and DT register settings
configs: socfpga: n5x: enable CMD_MTD
configs: socfpga: n5x: enable ISSI QSPI
arm: socfpga: n5x: switch firewall setup to driver model
arch: arm: dts: n5x: switch to using upstream Linux DT config
arm: socfpga: n5x: update SPL data save and restore implementation
arm: socfpga: soc64: separate reset manager into common and
platform-family parts
Dinesh Maniyam (10):
arch: arm: mach-socfpga: Change U-Boot mailbox client ID
arm: socfpga: Add NAND register address and data register
arm: arria10: Add correct mask bits for RTRIM and PU_DRV_STRG
arm: dts: socfpga: n5x: Drop kernel node from binman
arm: socfpga: Setting the image magic value to romcode
initswstate register
drivers: clk: altera: arria10: Fix wrong API used for memory free
drivers: fpga: arria10: Remove unreachable code.
arm: dts: socfpga_n5x_socdk: Enable watchdog0
arm: socfpga: Remove confusing timer related words from watchdog
reset
configs: socfpga: arria10: Disable CONFIG_SPL_USE_TINY_PRINTF
Marek Vasut (1):
MAINTAINERS: Replace Altera/SoCFPGA/Agilex with N:
Naresh Kumar Ravulapalli (1):
arch: arm: socfpga: Fix data cache flush issue
Peng Fan (1):
ddr: altera: Use dev_read_addr_index_ptr()
Tien Fong Chee (4):
arm: socfpga: Gen5/A10: Enable Designware watchdog
configs: socfpga_arria10_defconfig: Enable CONFIG_CMD_FPGA_LOADMK
arm: socfpga: n5x: use common soc64 env settings
arm: socfpga: cyclone5: select WDT with DESIGNWARE_WATCHDOG
tzeyeeng (1):
arm: dts: socfpga: Enable 8-bit embedded device support in
Agilex5 eMMC device tree
MAINTAINERS | 10 +-
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/socfpga_agilex-u-boot.dtsi | 6 -
arch/arm/dts/socfpga_agilex5.dtsi | 4 +
arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 10 +
arch/arm/dts/socfpga_agilex5_socdk_emmc.dts | 2 +-
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 56 +-
arch/arm/dts/socfpga_agilex_socdk_emmc-u-boot.dtsi | 16 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 56 +-
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 22 +-
arch/arm/dts/socfpga_n5x_socdk.dts | 122 ----
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 2 +
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 313 +++++++++++
arch/arm/dts/socfpga_stratix10.dtsi | 430 --------------
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 119 +++-
arch/arm/dts/socfpga_stratix10_socdk.dts | 143 -----
arch/arm/mach-socfpga/Kconfig | 33 +-
arch/arm/mach-socfpga/Makefile | 18 +-
arch/arm/mach-socfpga/clock_manager_s10.c | 448 ++-------------
arch/arm/mach-socfpga/config.mk | 39 +-
arch/arm/mach-socfpga/firewall.c | 107 ----
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 +
.../mach-socfpga/include/mach/clock_manager_s10.h | 175 +-----
arch/arm/mach-socfpga/include/mach/firewall.h | 69 ---
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 2 +-
.../include/mach/reset_manager_arria10.h | 2 +-
.../include/mach/system_manager_arria10.h | 2 +
arch/arm/mach-socfpga/misc.c | 37 +-
arch/arm/mach-socfpga/misc_arria10.c | 24 -
arch/arm/mach-socfpga/qts-filter-a10.sh | 4 +-
arch/arm/mach-socfpga/reset_manager_arria10.c | 4 +-
arch/arm/mach-socfpga/reset_manager_soc64.c | 80 +++
...anager_s10.c => reset_manager_soc64_families.c} | 81 +--
arch/arm/mach-socfpga/smc_api.c | 4 +-
arch/arm/mach-socfpga/spl_a10.c | 11 +-
arch/arm/mach-socfpga/spl_gen5.c | 17 +
arch/arm/mach-socfpga/spl_n5x.c | 32 +-
arch/arm/mach-socfpga/spl_s10.c | 70 ++-
board/altera/stratix10-socdk/Makefile | 6 +
board/altera/stratix10-socdk/socfpga.c | 12 +
board/intel/n5x-socdk/Makefile | 6 +
board/intel/n5x-socdk/socfpga.c | 12 +
cmd/Kconfig | 2 +-
configs/socfpga_agilex_defconfig | 2 +-
configs/socfpga_arria10_defconfig | 3 +
configs/socfpga_cyclone5_defconfig | 1 +
configs/socfpga_n5x_atf_defconfig | 89 ---
configs/socfpga_n5x_defconfig | 29 +-
configs/socfpga_n5x_vab_defconfig | 90 +--
configs/socfpga_stratix10_atf_defconfig | 90 ---
configs/socfpga_stratix10_defconfig | 69 +--
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-agilex.c | 9 -
drivers/clk/altera/clk-arria10.c | 7 +-
drivers/clk/altera/clk-n5x.c | 129 +++++
drivers/clk/altera/clk-n5x.h | 19 +
drivers/clk/altera/clk-s10.c | 616
+++++++++++++++++++++
drivers/clk/altera/clk-s10.h | 203 +++++++
drivers/ddr/altera/Makefile | 4 +-
drivers/ddr/altera/sdram_arria10.c | 32 +-
drivers/ddr/altera/sdram_gen5.c | 64 ++-
drivers/ddr/altera/sdram_s10.c | 60 +-
drivers/ddr/altera/sdram_soc32.c | 85 +++
drivers/ddr/altera/sdram_soc32.h | 15 +
drivers/ddr/altera/uibssm_mailbox.c | 2 +
drivers/fpga/socfpga_arria10.c | 2 -
drivers/mmc/socfpga_dw_mmc.c | 6 +-
dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts | 4 +
include/configs/socfpga_n5x_socdk.h | 33 --
69 files changed, 2164 insertions(+), 2114 deletions(-)
create mode 100644 arch/arm/dts/socfpga_agilex_socdk_emmc-u-boot.dtsi
delete mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts
delete mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
delete mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
delete mode 100644 arch/arm/mach-socfpga/firewall.c
create mode 100644 arch/arm/mach-socfpga/reset_manager_soc64.c
rename arch/arm/mach-socfpga/{reset_manager_s10.c =>
reset_manager_soc64_families.c} (76%)
create mode 100644 board/altera/stratix10-socdk/Makefile
create mode 100644 board/altera/stratix10-socdk/socfpga.c
create mode 100644 board/intel/n5x-socdk/Makefile
create mode 100644 board/intel/n5x-socdk/socfpga.c
delete mode 100644 configs/socfpga_n5x_atf_defconfig
delete mode 100644 configs/socfpga_stratix10_atf_defconfig
create mode 100644 drivers/clk/altera/clk-s10.c
create mode 100644 drivers/clk/altera/clk-s10.h
create mode 100644 drivers/ddr/altera/sdram_soc32.c
create mode 100644 drivers/ddr/altera/sdram_soc32.h
Best regards,
Tien Fong
prev parent reply other threads:[~2026-08-19 1:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-17 3:29 [GIT PULL] SoCFPGA updates for next (2026-08-17) Chee, Tien Fong via U-Boot
2026-08-17 18:27 ` Tom Rini
2026-08-18 4:04 ` Chee, Tien Fong
2026-08-18 16:32 ` Chee, Tien Fong
2026-08-18 16:35 ` Tom Rini
2026-08-18 20:17 ` Tom Rini
2026-08-19 1:16 ` Chee, Tien Fong [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=83d2b4a9-ae55-46cb-9dbd-9d603fa1ec94@altera.com \
--to=tien.fong.chee@altera.com \
--cc=alif.zakuan.yuslaimi@altera.com \
--cc=boon.khai.ng@altera.com \
--cc=briansune@gmail.com \
--cc=chen.huei.lok@altera.com \
--cc=dinesh.maniyam@altera.com \
--cc=marek.vasut+renesas@mailbox.org \
--cc=nareshkumar.ravulapalli@altera.com \
--cc=peng.fan@nxp.com \
--cc=trini@konsulko.com \
--cc=tzeyee.ng@altera.com \
--cc=u-boot@lists.u-boot-project.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.