From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9989275AFD for ; Tue, 18 Aug 2026 07:03:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787036621; cv=none; b=t3ZHgG1qKsYu+0XvAh1Nvv6A3A2ARdwTlMxhbEktb/0Vkj8YajbE3jWZBnw/eWyfEFOAKjAwVz9gOlszvbA5TrOUs+zUHDrbLcKTqzn1vNY/OHCf9nujqQ5my0mf8DSwtLnMNVi0MlrlelslDFHdFW3MmUlUFEI2jJ/+7j3NduA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787036621; c=relaxed/simple; bh=Vwyuh3vC0tpR+F8NSjiTjDkK0fgmA4qD3NcESazTbbg=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=QyuuhiPT/qgI1x05h7LfSVay6MBpiQ6Dnqkv1kdregW9uBoRn6XhPECMxG087926jEJoou+KuyXJg8QoZlCfmlYe9phGYw+qt/XCNpxivHq3lo2n20uQzfHP0v54T5uZ4DUdTHtzv7XkajYjV778T9uB71hVFSzznRhET37mBOw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e6nBxK3K; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e6nBxK3K" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BBE71F000E9; Tue, 18 Aug 2026 07:03:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787036619; bh=2yLLLSuBlVszJXUu80gALA+6IunTLE8SAePiRMTyfVY=; h=Date:Subject:From:To:Cc:References:In-Reply-To; b=e6nBxK3KeZ8ENjbdt2bubYxctEtaatVFqRjZKyQczssFpou9qU2PbZQEAUCOBXR3h uOczieO5X41wPrI3nG0TkRr7tZJpy6wIw0R7fIreygwH4LmK+IcEce2zbX06WEydTW ave3LA9+WLJjBjVLUMqtezNMGQEkNy3Cvm8pFT+E9HXKlWyH5lsRS9FJdkDxzMGy0A OSEtD3lrLg2ScBF/7blw0k+DLi2ACBHR0sTNYCNG5abf5DIkiLULyb26LUyVdQL9sX CtkUolproKQM+gUIFfYzjXRgiQYk9ubn4VzSnlewa1i2/hjRVqkPeu0qTsQhcvYt1n mNt9/SxPbxHJA== Message-ID: <83d95db0-75b6-4fbf-a8c2-3a7c2fd05bdd@kernel.org> Date: Tue, 18 Aug 2026 09:03:33 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding From: Krzysztof Kozlowski To: Tushar Nimkar Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, Michal Simek , Anirudha Sarangi , git-dev@amd.com References: <20260817105233.1557748-1-tushar.nimkar@amd.com> <20260818-smoky-jackalope-of-piety-7e4b21@quoll> Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 18/08/2026 09:03, Krzysztof Kozlowski wrote: > On Mon, Aug 17, 2026 at 04:22:33PM +0530, Tushar Nimkar wrote: >> From: Anirudha Sarangi >> >> Add a device tree binding schema for the Xilinx Versal NET SMMU CSR >> (Control and Status Register) interrupt controller. >> >> The SMMU CSR block acts as a vendor-specific interrupt controller >> in front of the ARM SMMUv3, providing registers to enable and clear >> standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ. >> Interrupts must be acknowledged in this block before being forwarded >> to the parent interrupt controller (e.g. GIC). >> >> Signed-off-by: Anirudha Sarangi >> Co-developed-by: Tushar Nimkar >> Signed-off-by: Tushar Nimkar >> --- > > b4 got only this one patch, where is the rest? > > Can finally people in AMD start using b4 to send patches? How many times > I need to ask for that? > > >> .../xlnx,versal-net-smmu-csr.yaml | 85 +++++++++++++++++++ >> 1 file changed, 85 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml >> >> +required: >> + - compatible >> + - reg >> + - interrupt-controller >> + - "#interrupt-cells" >> + - interrupts >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + >> + iommu@ec000000 { >> + compatible = "arm,smmu-v3"; >> + reg = <0xec000000 0x40000>; >> + #iommu-cells = <1>; >> + dma-coherent; >> + interrupt-names = "eventq", "gerror", "priq"; >> + interrupt-parent = <&smmu_irq_csr>; >> + interrupts = <0>, <2>, <3>; >> + }; > > Drop node irrelevant. > >> + >> + smmu_irq_csr: interrupt-controller@eca10000 { > > Drop unused label Ah and: drop second/last, redundant "bindings". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23 Best regards, Krzysztof