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From: Marek Vasut <marex@nabladev.com>
To: Frieder Schrempf <frieder.schrempf@kontron.de>,
	Frieder Schrempf <frieder@fris.de>,
	Stefano Babic <sbabic@nabladev.com>,
	Fabio Estevam <festevam@gmail.com>,
	Ilias Apalodimas <ilias.apalodimas@linaro.org>,
	Tom Rini <trini@konsulko.com>,
	u-boot@lists.u-boot-project.org
Cc: uboot-imx@nxp.com, Simona Toaca <simona.toaca@nxp.com>,
	Viorel Suman <viorel.suman@nxp.com>
Subject: Re: [PATCH v2 3/4] ddr: imx: Allow to call ddr init without logging failure
Date: Thu, 20 Aug 2026 17:25:39 +0200	[thread overview]
Message-ID: <83ee9efb-e09f-45d8-ac0a-cd9b2797c513@nabladev.com> (raw)
In-Reply-To: <fa652a2f-addc-47a4-b89e-755aba42509d@kontron.de>

On 8/20/26 4:25 PM, Frieder Schrempf wrote:
> On 20.08.26 10:05, Marek Vasut wrote:
>> On 8/20/26 8:34 AM, Frieder Schrempf wrote:
>>> On 19.08.26 14:47, Marek Vasut wrote:
>>>> On 8/19/26 12:10 PM, Frieder Schrempf wrote:
>>>>> On 19.08.26 12:04, Marek Vasut wrote:
>>>>>> On 8/19/26 9:07 AM, Frieder Schrempf wrote:
>>>>>>> From: Frieder Schrempf <frieder.schrempf@kontron.de>
>>>>>>>
>>>>>>> In some cases we need to call ddr_init() multiple times to try
>>>>>>> different configurations.
>>>>>>
>>>>>> What different configurations ? Details please ?
>>>>>
>>>>> The detection of different DDR types/sizes on our SoMs has always been
>>>>> based on trying the init and seeing if it succeeds, falling back to the
>>>>> smaller sizes on failure. See here [1].
>>>> Could you maybe bring the interface up in some minimal 400 MTps or 100
>>>> MTps configuration and then read out the MR ID registers from the DRAM
>>>> to discern which DRAM configuration is present on your SoM? This would
>>>> be the ideal generic way of doing this, and it would be reliable since
>>>> the IDs are stable and surely indicate which DRAM chip and how big it
>>>> is.
>>>
>>> No, unfortunately this doesn't work. We already tried. The MR ID can't
>>> be used as we have single and dual rank setups that report the same ID.
>>> We have no way of knowing how many dies are connected unless we try it.
>>
>> Is the controller unable to interact with each rank separately ? I would
>> expect in single rank setup, that read of MR ID from one rank would pass
>> and from the other rank it would fail ?
> 
> I'm not sure, but even if it would work, it would require several
> separate init attempts only to read the IDs

Why ? Init the bus in slowest mode with widest bus settings, then try 
MRRD on all available DRAM chips, then figure out which ones report 
valid IDs and which ones fail the MRd .

>, so I'm not sure if there is
> any benefit.

Generic solution that surely works and does not guess the DRAM size.

> Also I'm not seeing anyone doing this kind of thing. It
> might be worth looking at, but my primary goal now is to land patch 1 of
> this series in order to fix the regression.

What regression ? (I was not CCed on that)

You can (=should) send bugfixes separately.

  reply	other threads:[~2026-08-21  2:25 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-19  7:07 [PATCH v2 1/4] ddr: imx: Reload the training firmware for every PHY configuration Frieder Schrempf
2026-08-19  7:07 ` [PATCH v2 2/4] ddr: imx: Move error message for failed training to calling side Frieder Schrempf
2026-08-19  7:07 ` [PATCH v2 3/4] ddr: imx: Allow to call ddr init without logging failure Frieder Schrempf
2026-08-19 10:04   ` Marek Vasut
2026-08-19 10:10     ` Frieder Schrempf
2026-08-19 12:47       ` Marek Vasut
2026-08-20  6:34         ` Frieder Schrempf
2026-08-20  8:05           ` Marek Vasut
2026-08-20 14:25             ` Frieder Schrempf
2026-08-20 15:25               ` Marek Vasut [this message]
2026-08-19  7:07 ` [PATCH v2 4/4] imx: kontron-sl-mx8mm: Stop printing error message on first DDR init Frieder Schrempf

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