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To: Jan Beulich , "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Roger Pau =?ISO-8859-1?Q?Monn=E9?= Date: Thu, 13 Jun 2024 16:35:38 +0200 In-Reply-To: <82277592-ea96-47c8-a991-7afd97d7a7bc@suse.com> References: <82277592-ea96-47c8-a991-7afd97d7a7bc@suse.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.1 (3.52.1-1.fc40) MIME-Version: 1.0 On Thu, 2024-06-13 at 10:19 +0200, Jan Beulich wrote: > Intel CPUs have a MSR bit to limit CPUID enumeration to leaf two. If > this bit is set by the BIOS then CPUID evaluation does not work when > data from any leaf greater than two is needed; early_cpu_init() in > particular wants to collect leaf 7 data. >=20 > Cure this by unlocking CPUID right before evaluating anything which > depends on the maximum CPUID leaf being greater than two. >=20 > Inspired by (and description cloned from) Linux commit 0c2f6d04619e > ("x86/topology/intel: Unlock CPUID before evaluating anything"). >=20 > Signed-off-by: Jan Beulich Release-Acked-by: Oleksii Kurochko ~ Oleksii > --- > While I couldn't spot anything, it kind of feels as if I'm > overlooking > further places where we might be inspecting in particular leaf 7 yet > earlier. >=20 > No Fixes: tag(s), as imo it would be too many that would want > enumerating. >=20 > --- a/xen/arch/x86/cpu/common.c > +++ b/xen/arch/x86/cpu/common.c > @@ -336,7 +336,8 @@ void __init early_cpu_init(bool verbose) > =C2=A0 > =C2=A0 c->x86_vendor =3D x86_cpuid_lookup_vendor(ebx, ecx, edx); > =C2=A0 switch (c->x86_vendor) { > - case X86_VENDOR_INTEL:=C2=A0=C2=A0=C2=A0 actual_cpu =3D intel_cpu_dev;= =C2=A0=C2=A0=C2=A0 > break; > + case X86_VENDOR_INTEL:=C2=A0=C2=A0=C2=A0 intel_unlock_cpuid_leaves(c); > + =C2=A0 actual_cpu =3D intel_cpu_dev;=C2=A0=C2=A0=C2=A0 > break; > =C2=A0 case X86_VENDOR_AMD:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 actual_cpu =3D = amd_cpu_dev;=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > break; > =C2=A0 case X86_VENDOR_CENTAUR:=C2=A0 actual_cpu =3D centaur_cpu_dev;=C2= =A0 > break; > =C2=A0 case X86_VENDOR_SHANGHAI: actual_cpu =3D shanghai_cpu_dev; > break; > --- a/xen/arch/x86/cpu/cpu.h > +++ b/xen/arch/x86/cpu/cpu.h > @@ -24,3 +24,5 @@ void amd_init_lfence(struct cpuinfo_x86 > =C2=A0void amd_init_ssbd(const struct cpuinfo_x86 *c); > =C2=A0void amd_init_spectral_chicken(void); > =C2=A0void detect_zen2_null_seg_behaviour(void); > + > +void intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c); > --- a/xen/arch/x86/cpu/intel.c > +++ b/xen/arch/x86/cpu/intel.c > @@ -303,10 +303,24 @@ static void __init noinline intel_init_l > =C2=A0 ctxt_switch_masking =3D intel_ctxt_switch_masking; > =C2=A0} > =C2=A0 > -static void cf_check early_init_intel(struct cpuinfo_x86 *c) > +/* Unmask CPUID levels if masked. */ > +void intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c) > =C2=A0{ > - u64 misc_enable, disable; > + uint64_t misc_enable, disable; > + > + rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); > + > + disable =3D misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID; > + if (disable) { > + wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & > ~disable); > + bootsym(trampoline_misc_enable_off) |=3D disable; > + c->cpuid_level =3D cpuid_eax(0); > + printk(KERN_INFO "revised cpuid level: %u\n", c- > >cpuid_level); > + } > +} > =C2=A0 > +static void cf_check early_init_intel(struct cpuinfo_x86 *c) > +{ > =C2=A0 /* Netburst reports 64 bytes clflush size, but does IO in > 128 bytes */ > =C2=A0 if (c->x86 =3D=3D 15 && c->x86_cache_alignment =3D=3D 64) > =C2=A0 c->x86_cache_alignment =3D 128; > @@ -315,16 +329,7 @@ static void cf_check early_init_intel(st > =C2=A0 =C2=A0=C2=A0=C2=A0 bootsym(trampoline_misc_enable_off) & > MSR_IA32_MISC_ENABLE_XD_DISABLE) > =C2=A0 printk(KERN_INFO "re-enabled NX (Execute Disable) > protection\n"); > =C2=A0 > - /* Unmask CPUID levels and NX if masked: */ > - rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); > - > - disable =3D misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID; > - if (disable) { > - wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & > ~disable); > - bootsym(trampoline_misc_enable_off) |=3D disable; > - printk(KERN_INFO "revised cpuid level: %d\n", > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cpuid_eax(0)); > - } > + intel_unlock_cpuid_leaves(c); > =C2=A0 > =C2=A0 /* CPUID workaround for Intel 0F33/0F34 CPU */ > =C2=A0 if (boot_cpu_data.x86 =3D=3D 0xF && boot_cpu_data.x86_model =3D=3D= 3 > &&