From: Chris Wilson <chris@chris-wilson.co.uk>
To: Diego Celix <dcelix@gmail.com>,
intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [intel-gpu-tools][PATCH] Correct identification of the GEN5 chips on the IS_9XX() define
Date: Mon, 14 Feb 2011 15:59:09 +0000 [thread overview]
Message-ID: <849307$bignk4@azsmga001.ch.intel.com> (raw)
In-Reply-To: <AANLkTi=aUXnVRQ7ZT-Z6Z1HgT-15pMqY7YzuHAd6sV7g@mail.gmail.com>
On Mon, 14 Feb 2011 15:44:51 +0000, Diego Celix <dcelix@gmail.com> wrote:
> Hi,
>
> I've been trying to find the main cause because I got the following error:
>
> Couldn't map MMIO region: No such file or directory
Sigh. I wrote that off as another bug, since it was exactly the same
symptom as when changing the caching mode of the registers.
I applied a variant of that patch to remove IS_9XX instead.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
prev parent reply other threads:[~2011-02-14 15:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-14 15:44 [intel-gpu-tools][PATCH] Correct identification of the GEN5 chips on the IS_9XX() define Diego Celix
2011-02-14 15:59 ` Chris Wilson [this message]
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