* [PATCH 0/2] Enable DP MST encoders for SKL
@ 2014-12-12 14:26 Damien Lespiau
2014-12-12 14:26 ` [PATCH 1/2] drm/i915: Consolidate DDI clock reading out in a single function Damien Lespiau
2014-12-12 14:26 ` [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST Damien Lespiau
0 siblings, 2 replies; 6+ messages in thread
From: Damien Lespiau @ 2014-12-12 14:26 UTC (permalink / raw)
To: intel-gfx
The programming seems fairly similar to previous platforms, so let's create the
DP encoders on SKL as well.
--
Damien
Damien Lespiau (2):
drm/i915: Consolidate DDI clock reading out in a single function
drm/i915/skl: Skylake also supports DP MST
drivers/gpu/drm/i915/intel_ddi.c | 13 +++++++------
drivers/gpu/drm/i915/intel_dp.c | 2 +-
2 files changed, 8 insertions(+), 7 deletions(-)
--
1.8.3.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] drm/i915: Consolidate DDI clock reading out in a single function
2014-12-12 14:26 [PATCH 0/2] Enable DP MST encoders for SKL Damien Lespiau
@ 2014-12-12 14:26 ` Damien Lespiau
2014-12-12 14:26 ` [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST Damien Lespiau
1 sibling, 0 replies; 6+ messages in thread
From: Damien Lespiau @ 2014-12-12 14:26 UTC (permalink / raw)
To: intel-gfx
2 pieces of code need to read out the DDI clock: the DDI encoder and the
MST encoder .get_config() vfuncs.
Until now the SKL read out code was only in the former, so let's move
the pre and post SKL logic in intel_ddi_clock_get() and this this one
everywhere.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4e2e860..1c92ad4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -834,7 +834,12 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
{
- hsw_ddi_clock_get(encoder, pipe_config);
+ struct drm_device *dev = encoder->base.dev;
+
+ if (INTEL_INFO(dev)->gen <= 8)
+ hsw_ddi_clock_get(encoder, pipe_config);
+ else
+ skl_ddi_clock_get(encoder, pipe_config);
}
static void
@@ -2029,7 +2034,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
struct intel_hdmi *intel_hdmi;
u32 temp, flags = 0;
- struct drm_device *dev = dev_priv->dev;
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (temp & TRANS_DDI_PHSYNC)
@@ -2106,10 +2110,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
}
- if (INTEL_INFO(dev)->gen <= 8)
- hsw_ddi_clock_get(encoder, pipe_config);
- else
- skl_ddi_clock_get(encoder, pipe_config);
+ intel_ddi_clock_get(encoder, pipe_config);
}
static void intel_ddi_destroy(struct drm_encoder *encoder)
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST
2014-12-12 14:26 [PATCH 0/2] Enable DP MST encoders for SKL Damien Lespiau
2014-12-12 14:26 ` [PATCH 1/2] drm/i915: Consolidate DDI clock reading out in a single function Damien Lespiau
@ 2014-12-12 14:26 ` Damien Lespiau
2014-12-14 7:48 ` shuang.he
` (2 more replies)
1 sibling, 3 replies; 6+ messages in thread
From: Damien Lespiau @ 2014-12-12 14:26 UTC (permalink / raw)
To: intel-gfx
I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to
HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good
chance to be working as well as prevous platforms.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3fc3296..8e276c4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5085,7 +5085,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
intel_dp_aux_init(intel_dp, intel_connector);
/* init MST on ports that can support it */
- if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
if (port == PORT_B || port == PORT_C || port == PORT_D) {
intel_dp_mst_encoder_init(intel_dig_port,
intel_connector->base.base.id);
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST
2014-12-12 14:26 ` [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST Damien Lespiau
@ 2014-12-14 7:48 ` shuang.he
2014-12-14 20:39 ` Dave Airlie
2014-12-15 14:42 ` Daniel Vetter
2 siblings, 0 replies; 6+ messages in thread
From: shuang.he @ 2014-12-14 7:48 UTC (permalink / raw)
To: shuang.he, intel-gfx, damien.lespiau
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 364/364 364/364
ILK +3-2 362/366 363/366
SNB 448/450 448/450
IVB 497/498 497/498
BYT -2 289/289 287/289
HSW -1 563/564 562/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
ILK igt_kms_flip_nonexisting-fb DMESG_WARN(1, M26)PASS(4, M37M26) PASS(1, M26)
ILK igt_kms_flip_rcs-flip-vs-panning-interruptible DMESG_WARN(2, M26)PASS(3, M37M26) PASS(1, M26)
ILK igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible DMESG_WARN(1, M26)PASS(3, M26M37) PASS(1, M26)
*ILK igt_kms_flip_plain-flip-ts-check-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_wf_vblank-ts-check PASS(2, M26) DMESG_WARN(1, M26)
*BYT igt_drm_import_export_flink PASS(2, M48M50) DMESG_WARN(1, M50)
*BYT igt_drm_vma_limiter_gtt PASS(2, M48M50) TIMEOUT(1, M50)
*HSW igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked PASS(2, M40M19) DMESG_WARN(1, M19)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST
2014-12-12 14:26 ` [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST Damien Lespiau
2014-12-14 7:48 ` shuang.he
@ 2014-12-14 20:39 ` Dave Airlie
2014-12-15 14:42 ` Daniel Vetter
2 siblings, 0 replies; 6+ messages in thread
From: Dave Airlie @ 2014-12-14 20:39 UTC (permalink / raw)
To: Damien Lespiau; +Cc: intel-gfx@lists.freedesktop.org
On 13 December 2014 at 00:26, Damien Lespiau <damien.lespiau@intel.com> wrote:
> I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to
> HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good
> chance to be working as well as prevous platforms.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Seems like it should work to me, right until you release a gen 9 that
doesn't do MST,
but hopefully that won't happen, since 4k might matter even for the
atom chipsets.
Reviewed-by: Dave Airlie <airlied@redhat.com>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
> if (port == PORT_B || port == PORT_C || port == PORT_D) {
> intel_dp_mst_encoder_init(intel_dig_port,
> intel_connector->base.base.id);
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST
2014-12-12 14:26 ` [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST Damien Lespiau
2014-12-14 7:48 ` shuang.he
2014-12-14 20:39 ` Dave Airlie
@ 2014-12-15 14:42 ` Daniel Vetter
2 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2014-12-15 14:42 UTC (permalink / raw)
To: Damien Lespiau; +Cc: intel-gfx
On Fri, Dec 12, 2014 at 02:26:58PM +0000, Damien Lespiau wrote:
> I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to
> HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good
> chance to be working as well as prevous platforms.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3fc3296..8e276c4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5085,7 +5085,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> intel_dp_aux_init(intel_dp, intel_connector);
>
> /* init MST on ports that can support it */
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
HAS_DDI might be a nice bikeshed here if you're bored. Applied both to
dinq.
Thanks, Daniel
> if (port == PORT_B || port == PORT_C || port == PORT_D) {
> intel_dp_mst_encoder_init(intel_dig_port,
> intel_connector->base.base.id);
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-12-15 14:42 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-12-12 14:26 [PATCH 0/2] Enable DP MST encoders for SKL Damien Lespiau
2014-12-12 14:26 ` [PATCH 1/2] drm/i915: Consolidate DDI clock reading out in a single function Damien Lespiau
2014-12-12 14:26 ` [PATCH 2/2] drm/i915/skl: Skylake also supports DP MST Damien Lespiau
2014-12-14 7:48 ` shuang.he
2014-12-14 20:39 ` Dave Airlie
2014-12-15 14:42 ` Daniel Vetter
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