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2026 08:20:27.7186 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8fjGcJfM3V2s/lJQ0QfsH1o5r4Mc50uNdg1akSK19vR1Z0Z4Apm4UFNBDRXSa/RvkU3upyTf1tKYJrtMiHPWGg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB8200 X-OriginatorOrg: intel.com X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Intel-xe" X-Spam-Status: No, score=-7.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 28-10-2026 21:47, Andi Shyti wrote: > One more question here... > > ... > >> /* >> - * Hardware errors are reported through System Controller on the platforms that >> - * support it, and never routed as direct IRQ to SGUnit. So we should never be >> - * here for those platforms. >> + * Non fatal errors are routed as a direct IRQ on platforms that support >> + * system controller. >> */ >> if (xe->info.has_sysctrl) { >> - drm_err_ratelimited(&xe->drm, HW_ERR "Invalid error routing\n"); >> + drm_err_ratelimited(&xe->drm, HW_ERR "%s %s reported\n", hw_err_to_str(hw_err), >> + severity_str); >> + schedule_delayed_work(&tile->hw_error_work, msecs_to_jiffies(MSEC_PER_SEC)); > why are we waiting one second here? How did you choose this time? Its a best case scenario that if there is a non-fatal error which is accompanied with a fatal at the same time. We will wait for AER to get triggered to avoid unnecessary handling of non-fatal errors. It is not guaranteed that we will see a AER in 1sec because even that is a worker. If this is not okay, we can drop it as we are waiting for worker to complete anyway. Thanks Riana > > Andi