All of lore.kernel.org
 help / color / mirror / Atom feed
diff for duplicates of <8543411.nbQLj7Vctj@diego>

diff --git a/a/1.txt b/N1/1.txt
index 8e2c8e2..e976cfa 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,8 +1,8 @@
 Hi Daniel,
 
-Am Montag, 5. März 2018, 16:57:13 CET schrieb Daniel Schultz:
+Am Montag, 5. M?rz 2018, 16:57:13 CET schrieb Daniel Schultz:
 > On 03/05/2018 03:15 PM, Heiko Stuebner wrote:
-> > Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:
+> > Am Montag, 5. M?rz 2018, 13:45:11 CET schrieb Daniel Schultz:
 > >> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
 > >> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
 > >> 
diff --git a/a/content_digest b/N1/content_digest
index 3c14330..b212e8c 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,25 +1,17 @@
  "ref\01520253911-46218-1-git-send-email-d.schultz@phytec.de\0"
  "ref\03530074.WSbKf9j6h0@phil\0"
  "ref\0cecf3c08-d43d-c340-c5ff-30e41e338469@phytec.de\0"
- "From\0Heiko St\303\274bner <heiko@sntech.de>\0"
- "Subject\0Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing\0"
+ "From\0heiko@sntech.de (Heiko St\303\274bner)\0"
+ "Subject\0[PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing\0"
  "Date\0Mon, 05 Mar 2018 18:04:48 +0100\0"
- "To\0Daniel Schultz <d.schultz@phytec.de>\0"
- "Cc\0mark.rutland@arm.com"
-  devicetree@vger.kernel.org
-  linux@armlinux.org.uk
-  linux-kernel@vger.kernel.org
-  linux-rockchip@lists.infradead.org
-  robh+dt@kernel.org
-  w.egorov@phytec.de
- " linux-arm-kernel@lists.infradead.org\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "Hi Daniel,\n"
  "\n"
- "Am Montag, 5. M\303\244rz 2018, 16:57:13 CET schrieb Daniel Schultz:\n"
+ "Am Montag, 5. M?rz 2018, 16:57:13 CET schrieb Daniel Schultz:\n"
  "> On 03/05/2018 03:15 PM, Heiko Stuebner wrote:\n"
- "> > Am Montag, 5. M\303\244rz 2018, 13:45:11 CET schrieb Daniel Schultz:\n"
+ "> > Am Montag, 5. M?rz 2018, 13:45:11 CET schrieb Daniel Schultz:\n"
  "> >> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.\n"
  "> >> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.\n"
  "> >> \n"
@@ -74,4 +66,4 @@
  "> >>   \n"
  > >>   };
 
-9e5ecc52d13118f686b6a273a6775b1eeb76f4c81c58c5ff6cddd8938f82a5b2
+53e83179e62de24e63ec5a5d0cd494df8de8b07677fdeea4414a91a07245745d

diff --git a/a/content_digest b/N2/content_digest
index 3c14330..84b77a9 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -5,14 +5,14 @@
  "Subject\0Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing\0"
  "Date\0Mon, 05 Mar 2018 18:04:48 +0100\0"
  "To\0Daniel Schultz <d.schultz@phytec.de>\0"
- "Cc\0mark.rutland@arm.com"
-  devicetree@vger.kernel.org
+ "Cc\0robh+dt@kernel.org"
+  mark.rutland@arm.com
   linux@armlinux.org.uk
-  linux-kernel@vger.kernel.org
+  linux-arm-kernel@lists.infradead.org
   linux-rockchip@lists.infradead.org
-  robh+dt@kernel.org
-  w.egorov@phytec.de
- " linux-arm-kernel@lists.infradead.org\0"
+  devicetree@vger.kernel.org
+  linux-kernel@vger.kernel.org
+ " w.egorov@phytec.de\0"
  "\00:1\0"
  "b\0"
  "Hi Daniel,\n"
@@ -74,4 +74,4 @@
  "> >>   \n"
  > >>   };
 
-9e5ecc52d13118f686b6a273a6775b1eeb76f4c81c58c5ff6cddd8938f82a5b2
+0224ef0594dede35d4036a6839d2503c35cca3c10abaf1b6c994a9e968ac0e87

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.