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Sat, 19 Sep 2026 22:06:12 -0700 (PDT) Message-ID: <8572d404-8a33-4cd3-a14f-ebff7c2ac487@gmail.com> Date: Sun, 20 Sep 2026 13:05:58 +0800 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains To: fangyu.yu@linux.alibaba.com Cc: alex@ghiti.fr, andrew.jones@oss.qualcomm.com, anup@brainfault.org, aou@eecs.berkeley.edu, atish.patra@linux.dev, baolu.lu@linux.intel.com, gong.shuai@sanechips.com.cn, guoren@kernel.org, iommu@lists.linux.dev, jgg@nvidia.com, jgg@ziepe.ca, joerg.roedel@amd.com, joro@8bytes.org, jroedel@suse.de, kevin.tian@intel.com, kvm-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com, skhawaja@google.com, tomasz.jeznach@linux.dev, vasant.hegde@amd.com, will@kernel.org, zong.li@sifive.com References: <90826872-1374-49e4-832d-555abf8e8369@gmail.com> <20260920031259.20950-1-fangyu.yu@linux.alibaba.com> From: Gong Shuai In-Reply-To: <20260920031259.20950-1-fangyu.yu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Fangyu, On 9/20/2026 11:12 AM, fangyu.yu@linux.alibaba.com wrote: >>Hi Fangyu, >> >>On 9/15/2026 11:28 AM, fangyu.yu@linux.alibaba.com wrote: >>> From: Fangyu Yu >>> >>> Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when >>> attaching a second-stage domain, if the IOMMU supports AMO_HWAD. >>> >>> Software pre-populates second-stage page tables with D set, so >>> enabling GADE by default does not change normal behavior. When >>> dirty tracking is enabled, iommufd clears the pre-set D bits and >>> GADE becomes necessary for hardware to update the dirty bit on >>> write access. >>> >>> This avoids toggling GADE dynamically and keeps device context >>> setup consistent with second-stage domain attachment. >>> >>> Signed-off-by: Fangyu Yu >>> --- >>> drivers/iommu/riscv/iommu.c | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c >>> index 16779877351b..f01fd4e2f840 100644 >>> --- a/drivers/iommu/riscv/iommu.c >>> +++ b/drivers/iommu/riscv/iommu.c >>> @@ -1330,6 +1330,8 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, >>> FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) | >>> FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | >>> FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn); >>> + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD) >>> + dc.tc |= RISCV_IOMMU_DC_TC_GADE; > > Hi Shuai: > >> >>I might be missing something, but I don't see how the GADE bit set >>here reaches the hardware IOMMU DC. In riscv_iommu_iodir_update() >>(in patch 04/10), it looks like only the V bit is taken: >> >> tc = READ_ONCE(dc->tc); >> tc |= new_dc->ta & RISCV_IOMMU_DC_TC_V; >> ... >> WRITE_ONCE(dc->tc, tc); >> > > You’re right — this is a real issue. > > GADE was being set in the software-side dc, but it was not > propagated into the hardware DC in riscv_iommu_iodir_update(). > > I have already fixed this in my local tree, and I’ll include the > change in the next version of the patchset: > tc &= ~RISCV_IOMMU_DC_TC_GADE; > tc |= new_dc->tc & RISCV_IOMMU_DC_TC_GADE; > tc |= new_dc->ta & RISCV_IOMMU_DC_TC_V; > One thought here, instead of updating individual TC bits one by one in riscv_iommu_iodir_update(), could we transfer all software-configurable bits from the incoming DC to the hardware DC in one go? Something like: ... tc = (READ_ONCE(dc->tc) & ~GENMASK_ULL(11, 0)) | (new_dc->tc & GENMASK_ULL(11, 0)); ... WRITE_ONCE(dc->tc, tc); I’m not sure whether this could have negative side effects. >>I saw that you mentioned you tested it on QEMU. As far as I know, >>mainline QEMU has not yet declared the AMO_HWAD capability. Could >>you clarify whether you used a modified QEMU for this test? >> > > I used mainline QEMU, not a modified one. > > In QEMU, I only tested the second-stage path with a > VM using device passthrough. > > I did not test the dirty-log related part there, > so that path cannot be covered there. > > That is why I noted in the TODO that I will build a > dedicated test case for dirty log handling later. Sorry, I missed that TODO. Thanks, Shuai > > Thanks, > Fangyu > >>Thanks, >>Shuai >> >>> } else { >>> if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode)) >>> return -ENODEV; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9710C982CC for ; Sun, 20 Sep 2026 05:06:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: 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Pre-enable GADE for second-stage domains To: fangyu.yu@linux.alibaba.com Cc: alex@ghiti.fr, andrew.jones@oss.qualcomm.com, anup@brainfault.org, aou@eecs.berkeley.edu, atish.patra@linux.dev, baolu.lu@linux.intel.com, gong.shuai@sanechips.com.cn, guoren@kernel.org, iommu@lists.linux.dev, jgg@nvidia.com, jgg@ziepe.ca, joerg.roedel@amd.com, joro@8bytes.org, jroedel@suse.de, kevin.tian@intel.com, kvm-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com, skhawaja@google.com, tomasz.jeznach@linux.dev, vasant.hegde@amd.com, will@kernel.org, zong.li@sifive.com References: <90826872-1374-49e4-832d-555abf8e8369@gmail.com> <20260920031259.20950-1-fangyu.yu@linux.alibaba.com> From: Gong Shuai In-Reply-To: <20260920031259.20950-1-fangyu.yu@linux.alibaba.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260919_220614_731609_5A51175F X-CRM114-Status: GOOD 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Mozilla Thunderbird Subject: Re: [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains To: fangyu.yu@linux.alibaba.com Cc: alex@ghiti.fr, andrew.jones@oss.qualcomm.com, anup@brainfault.org, aou@eecs.berkeley.edu, atish.patra@linux.dev, baolu.lu@linux.intel.com, gong.shuai@sanechips.com.cn, guoren@kernel.org, iommu@lists.linux.dev, jgg@nvidia.com, jgg@ziepe.ca, joerg.roedel@amd.com, joro@8bytes.org, jroedel@suse.de, kevin.tian@intel.com, kvm-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com, skhawaja@google.com, tomasz.jeznach@linux.dev, vasant.hegde@amd.com, will@kernel.org, zong.li@sifive.com References: <90826872-1374-49e4-832d-555abf8e8369@gmail.com> <20260920031259.20950-1-fangyu.yu@linux.alibaba.com> From: Gong Shuai In-Reply-To: <20260920031259.20950-1-fangyu.yu@linux.alibaba.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260919_220614_509284_A1813A6E X-CRM114-Status: GOOD ( 27.21 ) X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org SGkgRmFuZ3l1LAoKT24gOS8yMC8yMDI2IDExOjEyIEFNLCBmYW5neXUueXVAbGludXguYWxpYmFi YS5jb20gd3JvdGU6Cj4+SGkgRmFuZ3l1LAo+Pgo+Pk9uIDkvMTUvMjAyNiAxMToyOCBBTSwgZmFu Z3l1Lnl1QGxpbnV4LmFsaWJhYmEuY29tIHdyb3RlOgo+Pj4gRnJvbTogRmFuZ3l1IFl1IDxmYW5n eXUueXVAbGludXguYWxpYmFiYS5jb20+Cj4+Pgo+Pj4gUHJlLWVuYWJsZSBSSVNDVl9JT01NVV9E Q19UQ19HQURFIGluIHRoZSBkZXZpY2UgY29udGV4dCB3aGVuCj4+PiBhdHRhY2hpbmcgYSBzZWNv bmQtc3RhZ2UgZG9tYWluLCBpZiB0aGUgSU9NTVUgc3VwcG9ydHMgQU1PX0hXQUQuCj4+Pgo+Pj4g U29mdHdhcmUgcHJlLXBvcHVsYXRlcyBzZWNvbmQtc3RhZ2UgcGFnZSB0YWJsZXMgd2l0aCBEIHNl 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