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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000A347.mail.protection.outlook.com (10.167.244.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8922.22 via Frontend Transport; Tue, 15 Jul 2025 08:59:00 +0000 Received: from BLR-L1-NDADHANI (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 15 Jul 2025 03:58:57 -0500 From: Nikunj A Dadhania To: Borislav Petkov CC: Sean Christopherson , Tom Lendacky , , , , , , Subject: Re: [PATCH] x86/sev: Improve handling of writes to intercepted GUEST_TSC_FREQ In-Reply-To: <20250715084357.GCaHYUzeqvBxJyGVsg@fat_crate.local> References: <20250711041200.87892-1-nikunj@amd.com> <20250714104424.GGaHTfiFxI_pf-vhRn@fat_crate.local> <76e0988d-279f-be58-51d9-621806dbb453@amd.com> <20250714161639.GLaHUtZwleS3COfxxX@fat_crate.local> <85jz49x31p.fsf@amd.com> <20250715084357.GCaHYUzeqvBxJyGVsg@fat_crate.local> Date: Tue, 15 Jul 2025 08:58:49 +0000 Message-ID: <85h5zdx22e.fsf@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A347:EE_|SA1PR12MB5670:EE_ X-MS-Office365-Filtering-Correlation-Id: 385202b7-8a39-4d14-a84d-08ddc37dd737 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2025 08:59:00.4895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 385202b7-8a39-4d14-a84d-08ddc37dd737 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5670 Borislav Petkov writes: > On Tue, Jul 15, 2025 at 08:37:38AM +0000, Nikunj A Dadhania wrote: >> Currently, when a Secure TSC enabled SNP guest attempts to write to >> the intercepted GUEST_TSC_FREQ MSR (a read-only MSR), the guest kernel >> #VC handler terminates the SNP guest by returning ES_VMM_ERROR. This >> response incorrectly implies a VMM configuration error, when in fact >> it's a valid VMM configuration to intercept writes to read-only MSRs, > > Not only valid - it is the usual thing the HV does with MSRs IMHO. Right, will update > >> unless explicitly documented. >> >> Modify the intercepted GUEST_TSC_FREQ MSR #VC handler to ignore writes >> instead of terminating the guest. Since GUEST_TSC_FREQ is a guest-only >> MSR, ignoring writes directly (rather than forwarding to the VMM and >> handling the resulting #GP) eliminates a round trip to the VMM. > > Probably. > > But I think the main point here is that this is the default action the HV > does. Correct, to adhere to that behaviour, I had sent the following patch earlier [1]. If GUEST_TSC_FREQ is intercepted by VMM: MSR read will terminate the guest, same behavior as earlier. MSR write will be passed to the VMM and VMM will inject the GP# back. > >> Add a >> WARN_ONCE to log the incident, as well-behaved guest kernels should >> never attempt to write to this read-only MSR. >> >> However, continue to terminate the guest(via ES_VMM_ERROR) when > > ES_EXCEPTION Are you suggesting to change the intercepted GUEST_TSC_FREQ MSR read behaviour from panic to ES_EXCEPTION? > >> reading from intercepted GUEST_TSC_FREQ MSR with Secure TSC enabled, >> as intercepted reads indicate an improper VMM configuration for Secure >> TSC enabled SNP guests. > > It is getting close to the gist of what we talked yesterday tho. Ack Regards, Nikunj 1. https://lore.kernel.org/kvm/85h5zkuxa2.fsf@amd.com/