From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 491BDC02196 for ; Wed, 5 Feb 2025 01:57:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EE59610E130; Wed, 5 Feb 2025 01:57:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aoghvaZ3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id B57D710E717 for ; Wed, 5 Feb 2025 01:57:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738720639; x=1770256639; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=0b+VlVngQSqCGe48trhVxLXoSn35WyCQmskIMxDTBXI=; b=aoghvaZ3P1EBzdJ+pGFzy3iMXvTzyVxV1450K+VHSkWvA0Hk30zBvhv2 tdHGocPgKm31k6FJbANZSocaJ2yArb40ZkhN+ZOjWzjh9dekc+kVrBank 5dZaxjTPIqAHicIl7pLjHpnazGR1JZYNCdDp1KAMpgZ20LX3M+YAk+V1+ 8xbUSwf78arFu4VdVa6Rmyqo29u9znQe4hIdwRwv34JvN2hqVdVTPq4dI Mv7MT9TcqTM0mZ8ZoMCN1GFvio1bPErponr3MXaKWx/1Ea6mVE5T2tUHo QfgsoASE+bC/xg1S/367JAd2gXtl1bqEMQ60poUI9f8AHO+ce/gFbOGY3 g==; X-CSE-ConnectionGUID: tqNi8NI3RXCOBfVcd8Vaaw== X-CSE-MsgGUID: tG2SvRpcQniU5TbeuQXOpw== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="56698894" X-IronPort-AV: E=Sophos;i="6.13,260,1732608000"; d="scan'208";a="56698894" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2025 17:57:18 -0800 X-CSE-ConnectionGUID: 92KHjfIhTvuBsV8h4OUQZg== X-CSE-MsgGUID: wldOq3ypRfylRKAJ/P8j2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,260,1732608000"; d="scan'208";a="115802259" Received: from orsosgc001.jf.intel.com (HELO orsosgc001.intel.com) ([10.165.21.142]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2025 17:57:18 -0800 Date: Tue, 04 Feb 2025 17:57:17 -0800 Message-ID: <85msf1dugy.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: "Olson, Matthew" Cc: Harish Chegondi , Subject: Re: [PATCH v8 5/7] drm/xe/eustall: Add EU stall sampling support for Xe2 In-Reply-To: References: <855xlwgasx.wl-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-redhat-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Tue, 04 Feb 2025 17:16:00 -0800, Olson, Matthew wrote: > Hi Matt, > On Wed, Jan 29, 2025 at 08:55:42PM -0800, Dixit, Ashutosh wrote: > > On Wed, 15 Jan 2025 12:02:11 -0800, Harish Chegondi wrote: > > > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c > > > index 437782f8433c..d72f80a9dfe4 100644 > > > --- a/drivers/gpu/drm/xe/xe_eu_stall.c > > > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c > > > @@ -73,6 +73,42 @@ struct xe_eu_stall_data_pvc { > > > __u64 unused[6]; > > > } __packed; > > > > > > +/** > > > + * struct xe_eu_stall_data_xe2 - EU stall data format for LNL, BMG > > > + * > > > + * Bits Field > > > + * 0 to 28 IP (addr) > > > + * 29 to 36 Tdr count > > > + * 37 to 44 other count > > > + * 45 to 52 control count > > > + * 53 to 60 pipestall count > > > + * 61 to 68 send count > > > + * 69 to 76 dist_acc count > > > + * 77 to 84 sbid count > > > + * 85 to 92 sync count > > > + * 93 to 100 inst_fetch count > > > + * 101 to 108 Active count > > > + * 109 to 111 Exid > > > + * 112 EndFlag (is always 1) > > > + */ > > > +struct xe_eu_stall_data_xe2 { > > > + __u64 ip_addr:29; > > > + __u64 tdr_count:8; > > > + __u64 other_count:8; > > > + __u64 control_count:8; > > > + __u64 pipestall_count:8; > > > + __u64 send_count:8; > > > + __u64 dist_acc_count:8; > > > + __u64 sbid_count:8; > > > + __u64 sync_count:8; > > > + __u64 inst_fetch_count:8; > > > + __u64 active_count:8; > > > + __u64 ex_id:3; > > > + __u64 end_flag:1; > > > + __u64 unused_bits:15; > > > + __u64 unused[6]; > > > +} __packed; > > > > Same question about whether or not to retain this struct. Retain it if we > > want to document this information otherwise drop it and just keep sizeof. > > I'd prefer to keep them, as I've personally found it convenient to refer > to them while while writing the userspace reader of these samples. I'm not > aware of any other particular place that they can be found, other than > maybe some other public repo that uses the i915 version of this interface > (IGT, maybe?). I'd venture to guess that others trying to call this > code are also going to be searching for these definitions in > `drivers/gpu/drm/xe` as well. Yes, they are present in the IGT's too: https://patchwork.freedesktop.org/patch/630656/?series=143030&rev=1 Would that work for you, or you prefer them in the kernel? Just trying to get an idea right now, not deciding one way or another. Thanks. -- Ashutosh > > > > > > + > > > static u64 per_xecore_buf_size = SZ_512K; > > > > > > static unsigned long > > > @@ -83,6 +119,8 @@ xe_eu_stall_data_record_size(struct xe_device *xe) > > > > > > if (platform == XE_PVC) > > > record_size = sizeof(struct xe_eu_stall_data_pvc); > > > + else if ((platform == XE_LUNARLAKE) || (platform == XE_BATTLEMAGE)) > > > > 'else if (GRAPHICS_VER(xe) >= 20)' so that we don't have to keep adding > > each individual platform. > > > > > + record_size = sizeof(struct xe_eu_stall_data_xe2); > > > > > > return record_size; > > > } > > > @@ -311,10 +349,16 @@ eu_stall_data_buf_check(struct xe_eu_stall_data_stream *stream) > > > static void > > > clear_dropped_eviction_line_bit(struct xe_gt *gt, u16 group, u16 instance) > > > { > > > + struct xe_device *xe = gt_to_xe(gt); > > > u32 write_ptr_reg; > > > > > > - /* On PVC, the overflow bit has to be cleared by writing 1 to it. */ > > > - write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP); > > > + /* On PVC, the overflow bit has to be cleared by writing 1 to it. > > > + * On other GPUs, the bit has to be cleared by writing 0 to it. > > > + */ > > > + if (GRAPHICS_VER(xe) >= 20) > > > + write_ptr_reg = _MASKED_BIT_DISABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP); > > > + else > > > + write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP); > > > > > > xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT, write_ptr_reg, group, instance); > > > } > > > @@ -882,7 +926,9 @@ static const struct file_operations fops_eu_stall = { > > > > > > static inline bool has_eu_stall_sampling_support(struct xe_device *xe) > > > { > > > - return ((xe->info.platform == XE_PVC) ? true : false); > > > + return ((xe->info.platform == XE_PVC || > > > + xe->info.platform == XE_LUNARLAKE || > > > + xe->info.platform == XE_BATTLEMAGE) ? true : false); > > > > Same here, use (GRAPHICS_VER(xe) >= 20). > > > > > } > > > > > > /** > > > -- > > > 2.47.1 > > >