From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: <intel-xe@lists.freedesktop.org>, <saurabhg.gupta@intel.com>,
<alex.zuo@intel.com>, <umesh.nerlige.ramappa@intel.com>,
<john.c.harrison@intel.com>, <matthew.d.roper@intel.com>,
<lucas.demarchi@intel.com>
Subject: Re: [PATCH v3] drm/xe/xe_guc_ads: Add nonpriv registers to write list
Date: Mon, 02 Dec 2024 12:33:24 -0800 [thread overview]
Message-ID: <85ttbl3jvv.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20241122180826.7075-1-jonathan.cavitt@intel.com>
On Fri, 22 Nov 2024 10:08:26 -0800, Jonathan Cavitt wrote:
>
> When performing a guc_mmio_regset_write, we add all the registers in the
> reg_sr list to the save/restore list, but do not do the same for the
> nonpriv registers. Add them in.
>
> v2:
> - Add all NONPRIV registers to avoid undefined behavior (Harrison)
> - s/whitelist/nonpriv
>
> v3:
> - Rebase
>
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2249
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> CC: Lucas de Marchi <lucas.demarchi@intel.com>
> CC: Matt Roper <matthew.d.roper@intel.com>
> CC: John Harrison <john.c.harrison@intel.com>
> CC: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> CC: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_ads.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 943146e5b460..b0afb89d9d90 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -243,6 +243,8 @@ static size_t calculate_regset_size(struct xe_gt *gt)
> xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry)
> count++;
>
> + count += RING_MAX_NONPRIV_SLOTS * XE_NUM_HW_ENGINES;
> +
> count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;
>
> if (XE_WA(gt, 1607983814))
> @@ -727,6 +729,11 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
> xa_for_each(&hwe->reg_sr.xa, idx, entry)
> guc_mmio_regset_write_one(ads, regset_map, entry->reg, count++);
>
> + for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
> + guc_mmio_regset_write_one(ads, regset_map,
> + RING_FORCE_TO_NONPRIV(hwe->mmio_base, i),
> + count++);
> +
What about the EU_PERF_CNTL registers which were there in the original
patch? Those are not needed?
> for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) {
> if (e->skip)
> continue;
> --
> 2.43.0
>
next prev parent reply other threads:[~2024-12-02 20:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-22 18:08 [PATCH v3] drm/xe/xe_guc_ads: Add nonpriv registers to write list Jonathan Cavitt
2024-11-22 18:13 ` ✓ CI.Patch_applied: success for drm/xe/xe_guc_ads: Add nonpriv registers to write list (rev3) Patchwork
2024-11-22 18:13 ` ✓ CI.checkpatch: " Patchwork
2024-11-22 18:15 ` ✓ CI.KUnit: " Patchwork
2024-11-22 18:33 ` ✓ CI.Build: " Patchwork
2024-11-22 18:35 ` ✓ CI.Hooks: " Patchwork
2024-11-22 18:37 ` ✓ CI.checksparse: " Patchwork
2024-11-22 19:01 ` ✓ Xe.CI.BAT: " Patchwork
2024-11-24 1:43 ` ✗ Xe.CI.Full: failure " Patchwork
2024-12-02 20:33 ` Dixit, Ashutosh [this message]
2024-12-02 21:11 ` [PATCH v3] drm/xe/xe_guc_ads: Add nonpriv registers to write list Cavitt, Jonathan
2024-12-03 21:53 ` Dixit, Ashutosh
2024-12-03 22:11 ` Lucas De Marchi
2024-12-06 17:06 ` Dixit, Ashutosh
2024-12-06 17:22 ` Lucas De Marchi
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