From: "Keith Packard" <keithp@keithp.com>
To: "drivers, Intel" <Intel-gfx@lists.freedesktop.org>
Subject: Is MI_FLUSH_ENABLE bit 12?
Date: Mon, 28 Nov 2011 18:48:04 -0800 [thread overview]
Message-ID: <861usr63vf.fsf@sumi.keithp.com> (raw)
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Just reading through vol1c.4 of the bspec this evening and found something odd.
Bit 11 of MI_MODE is "Invalidate UHPTR enable".
Bit 12 of MI_MODE is "MI_FLUSH Enable"
And, yet, in i915_reg.h:
#define MI_MODE 0x0209c
# define VS_TIMER_DISPATCH (1 << 6)
# define MI_FLUSH_ENABLE (1 << 11)
Are we off-by-one on MI_FLUSH_ENABLE? Seems like this would cause
serious problems...
--
keith.packard@intel.com
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next reply other threads:[~2011-11-29 23:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-11-29 2:48 Keith Packard [this message]
2011-11-30 0:47 ` Is MI_FLUSH_ENABLE bit 12? Eric Anholt
2011-11-30 3:42 ` Ben Widawsky
2011-11-30 8:08 ` Keith Packard
2011-11-30 21:54 ` Eric Anholt
2011-12-05 22:57 ` Jesse Barnes
2011-12-06 19:56 ` Eric Anholt
2011-12-06 20:21 ` Jesse Barnes
2011-12-06 21:04 ` Daniel Vetter
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